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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Features
NAND Flash Memory
MT29F16G08ABABA, MT29F32G08AFABA, MT29F64G08A[J/K/M]ABA, MT29F128G08AUABA, MT29F16G08ABCBB, MT29F32G08AECBB, MT29F64G08A[K/M]CBB, MT29F128G08AUCBB Features
* Open NAND Flash Interface (ONFI) 2.1-compliant1 * Single-level cell (SLC) technology * Organization - Page size x8: 4320 bytes (4096 + 224 bytes) - Block size: 128 pages (512K +28K bytes) - Plane size: 2 planes x 2048 blocks per plane - Device size: 16Gb: 4096 blocks; 32Gb: 8192 blocks; 64Gb: 16,384 blocks; 128Gb: 32,768 blocks * Synchronous I/O performance - Up to synchronous timing mode 4 - Clock rate: 12ns (DDR) - Read/write throughput per pin: 166 MT/s * Asynchronous I/O performance - Up to asynchronous timing mode 4 - tRC/tWC: 25ns (MIN) * Array performance - Read page: 25s (MAX) - Program page: 230s (TYP) - Erase block: 700s (TYP) * Operating Voltage Range - VCC: 2.7-3.6V - VCCQ: 1.7-1.95V, 2.7-3.6V * Command set: ONFI NAND Flash Protocol * Advanced Command Set - Program cache - Read cache sequential - Read cache random - One-time programmable (OTP) mode - Multi-plane commands - Multi-LUN operations - Read unique ID - Copyback * First block (block address 00h) is valid when shipped from factory. www..comFor minimum required ECC, see Error Management (page 107). * RESET (FFh) required as first command after poweron * Operation status byte provides software method for detecting - Operation completion - Pass/fail condition - Write-protect status * Data strobe (DQS) signals provide a hardware method for synchronizing data DQ in the synchronous interface * Copyback operations supported within the plane from which data is read * Quality and reliability - Data retention: 10 years - Endurance: 100,000 PROGRAM/ERASE cycles * Operating temperature: - Commercial: 0C to +70C - Industrial (IT): -40C to +85C * Package - 52-pad LGA - 48-pin TSOP - 100-ball BGA
Note: 1. The ONFI 2.1 specification is available at www.onfi.org.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Features Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron's part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. Figure 1: Part Numbering
MT 29F 16G 08 Micron Technology NAND Flash
29F = NAND Flash memory
A
B
A
B
A
WP
ES
:B Design Revision
B = Second revision
Production Status
Blank = Production ES = Engineering sample
Density
16G = 16Gb 32G = 32Gb 64G = 64Gb 128G = 128Gb
Reserved for Future Use Blank Operating Temperature Range
Blank = Commercial (0C to +70C) IT = Industrial (-40C to +85C)
Device Width
08 = 8 bits
Level
Bit/Cell A 1-bit
Speed Grade (synchronous mode only)
-12 = 166 MT/s
Classification
Die # of CE# # of R/B# I/O B E F J K M U 1 2 2 4 4 4 8 1 2 2 2 2 4 4 1 2 2 2 2 4 4 Common Separate Common Common Separate Separate Separate
Package Code
C5 = 52-pad VLGA 14mm x 18mm x 1.0mm1 H1 = 100-ball VBGA 12mm x 18mm x 1.0mm1 H2 = 100-ball TBGA 12mm x 18mm x 1.2mm1 H3 = 100-ball LBGA 12mm x 18mm x 1.4mm1 WP = 48-pin TSOP1 (CPL)
Interface
A = Async only B = Sync/Async
Generation Feature Set
A = VCC: 3.3V (2.7-3.6V), VCCQ: 3.3V (2.7-3.6V) C = VCC: 3.3V (2.7-3.6V), VCCQ: 1.8V (1.7-1.95V)
Operating Voltage Range
B = Second set of device features
Note:
1. Pb-free package.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
General Description ......................................................................................................................................... 9 Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9 Signal Assignments ......................................................................................................................................... 11 Package Dimensions ...................................................................................................................................... 14 Architecture ................................................................................................................................................... 19 Device and Array Organization ....................................................................................................................... 20 Bus Operation - Asynchronous Interface ........................................................................................................ 28 Asynchronous Enable/Standby ................................................................................................................... 28 Asynchronous Bus Idle ............................................................................................................................... 28 Asynchronous Commands .......................................................................................................................... 29 Asynchronous Addresses ............................................................................................................................ 30 Asynchronous Data Input ........................................................................................................................... 31 Asynchronous Data Output ........................................................................................................................ 32 Write Protect .............................................................................................................................................. 33 Ready/Busy# .............................................................................................................................................. 33 Bus Operation - Synchronous Interface ........................................................................................................... 38 Synchronous Enable/Standby ..................................................................................................................... 39 Synchronous Bus Idle/Driving .................................................................................................................... 39 Synchronous Commands ........................................................................................................................... 40 Synchronous Addresses .............................................................................................................................. 41 Synchronous DDR Data Input ..................................................................................................................... 42 Synchronous DDR Data Output .................................................................................................................. 43 Write Protect .............................................................................................................................................. 45 Ready/Busy# .............................................................................................................................................. 45 Device Initialization ....................................................................................................................................... 46 Activating Interfaces ....................................................................................................................................... 47 Activating the Asynchronous Interface ........................................................................................................ 47 Activating the Synchronous Interface .......................................................................................................... 47 Command Definitions .................................................................................................................................... 49 Reset Operations ............................................................................................................................................ 51 RESET (FFh) ............................................................................................................................................... 51 SYNCHRONOUS RESET (FCh) .................................................................................................................... 52 Identification Operations ................................................................................................................................ 53 READ ID (90h) ............................................................................................................................................ 53 READ ID Parameter Tables ............................................................................................................................. 54 Configuration Operations ............................................................................................................................... 55 SET FEATURES (EFh) ................................................................................................................................. 55 GET FEATURES (EEh) ................................................................................................................................. 56 READ PARAMETER PAGE (ECh) ...................................................................................................................... 60 Parameter Page Data Structure Tables ............................................................................................................. 61 READ UNIQUE ID (EDh) ................................................................................................................................ 70 Status Operations ........................................................................................................................................... 71 READ STATUS (70h) ................................................................................................................................... 72 READ STATUS ENHANCED (78h) ............................................................................................................... 73 Column Address Operations ........................................................................................................................... 74 www..com CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 74 CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 75 CHANGE WRITE COLUMN (85h) ................................................................................................................ 76 CHANGE ROW ADDRESS (85h) ................................................................................................................... 77 Read Operations ............................................................................................................................................. 79
Contents
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
READ MODE (00h) ..................................................................................................................................... 81 READ PAGE (00h-30h) ................................................................................................................................ 82 READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 83 READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 84 READ PAGE CACHE LAST (3Fh) .................................................................................................................. 86 READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 87 Program Operations ....................................................................................................................................... 89 PROGRAM PAGE (80h-10h) ........................................................................................................................ 89 PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 91 PROGRAM PAGE MULTI-PLANE 80h-11h ................................................................................................... 93 Erase Operations ............................................................................................................................................ 95 ERASE BLOCK (60h-D0h) ............................................................................................................................ 95 ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 96 Copyback Operations ..................................................................................................................................... 97 COPYBACK READ (00h-35h) ....................................................................................................................... 98 COPYBACK PROGRAM (85h-10h) ............................................................................................................... 99 COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 99 COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 100 One-Time Programmable (OTP) Operations ................................................................................................... 101 PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 102 PROTECT OTP AREA (80h-10h) .................................................................................................................. 103 READ OTP PAGE (00h-30h) ........................................................................................................................ 104 Multi-Plane Operations ................................................................................................................................. 105 Multi-Plane Addressing ............................................................................................................................. 105 Interleaved Die (Multi-LUN) Operations ........................................................................................................ 106 Error Management ........................................................................................................................................ 107 Output Drive Impedance ............................................................................................................................... 108 AC Overshoot/Undershoot Specifications ...................................................................................................... 111 Synchronous Input Slew Rate ........................................................................................................................ 112 Output Slew Rate ........................................................................................................................................... 113 Electrical Specifications ................................................................................................................................. 114 Electrical Specifications - DC Characteristics and Operating Conditions (Asynchronous) ................................. 116 Electrical Specifications - DC Characteristics and Operating Conditions (Synchronous) .................................. 117 Electrical Specifications - DC Characteristics and Operating Conditions (VCCQ) ............................................... 117 Electrical Specifications - AC Characteristics and Operating Conditions (Asynchronous) ................................. 118 Electrical Specifications - AC Characteristics and Operating Conditions (Synchronous) ................................... 120 Electrical Specifications - Array Characteristics .............................................................................................. 123 Asynchronous Interface Timing Diagrams ...................................................................................................... 124 Synchronous Interface Timing Diagrams ........................................................................................................ 135 Revision History ............................................................................................................................................ 157 Rev. E, Production - 3/10 ........................................................................................................................... 157 Rev. D, Production - 1/10 .......................................................................................................................... 157 Rev. C - 9/09 ............................................................................................................................................. 157 Rev. B - 2/09 ............................................................................................................................................. 157 Rev. A - 1/09 ............................................................................................................................................. 158
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9 Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 27 Table 3: Asynchronous Interface Mode Selection ........................................................................................... 28 Table 4: Synchronous Interface Mode Selection ............................................................................................. 38 Table 5: Command Set .................................................................................................................................. 49 Table 6: Read ID Parameters for Address 00h ................................................................................................. 54 Table 7: Read ID Parameters for Address 20h .................................................................................................. 54 Table 8: Feature Address Definitions .............................................................................................................. 55 Table 9: Feature Address 01h: Timing Mode ................................................................................................... 57 Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 57 Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 58 Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 58 Table 13: Parameter Page Data Structure ....................................................................................................... 61 Table 14: Status Register Definition ............................................................................................................... 71 Table 15: OTP Area Details ........................................................................................................................... 102 Table 16: Error Management Details ............................................................................................................. 107 Table 17: Output Drive Strength Test Conditions (VCCQ = 1.7-1.95V) .............................................................. 108 Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7-1.95V) .......................................................... 108 Table 19: Output Drive Strength Conditions (VCCQ = 2.7-3.6V) ....................................................................... 109 Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7-3.6V) ............................................................ 109 Table 21: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 110 Table 22: Overshoot/Undershoot Parameters ................................................................................................ 111 Table 23: Test Conditions for Input Slew Rate ................................................................................................ 112 Table 24: Input Slew Rate (VCCQ = 1.7-1.95V) ................................................................................................. 112 Table 25: Test Conditions for Output Slew Rate ............................................................................................. 113 Table 26: Output Slew Rate (VCCQ = 1.7-1.95V) .............................................................................................. 113 Table 27: Output Slew Rate (VCCQ = 2.7-3.6V) ................................................................................................ 113 Table 28: Absolute Maximum Ratings by Device ............................................................................................ 114 Table 29: Recommended Operating Conditions ............................................................................................ 114 Table 30: Valid Blocks per LUN ..................................................................................................................... 114 Table 31: Capacitance: 100-Ball BGA Package ................................................................................................ 115 Table 32: Capacitance: 48-Pin TSOP Package ................................................................................................ 115 Table 33: Capacitance: 52-Pad LGA Package .................................................................................................. 115 Table 34: Test Conditions ............................................................................................................................. 116 Table 35: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 116 Table 36: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 117 Table 37: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 117 Table 38: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 118 Table 39: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 118 Table 40: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 120 Table 41: Array Characteristics ..................................................................................................................... 123
List of Tables
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Figure 1: Part Numbering ................................................................................................................................ 2 Figure 2: 48-Pin TSOP Type 1 (Top View) ....................................................................................................... 11 Figure 3: 52-Pad LGA (Top View) ................................................................................................................... 12 Figure 4: 100-Ball BGA (Ball-Down, Top View) ................................................................................................ 13 Figure 5: 48-Pin TSOP - Type 1 CPL (Package Code: WP) ................................................................................ 14 Figure 6: 52-Pad VLGA .................................................................................................................................. 15 Figure 7: 100-Ball VBGA - 12mm x 18mm (Package Code: H1) ......................................................................... 16 Figure 8: 100-Ball TBGA - 12mm x 18mm (Package Code: H2) ......................................................................... 17 Figure 9: 100-Ball LBGA - 12mm x 18mm (Package Code: H3) ......................................................................... 18 Figure 10: NAND Flash Die (LUN) Functional Block Diagram ......................................................................... 19 Figure 11: Device Organization for Single-Die Package (TSOP/BGA) ............................................................... 20 Figure 12: Device Organization for Two-Die Package (TSOP) .......................................................................... 21 Figure 13: Device Organization for Two-Die Package (BGA) ............................................................................ 22 Figure 14: Device Organization for Four-Die Package (TSOP) .......................................................................... 23 Figure 15: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA) ...................................... 24 Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA) .................. 25 Figure 17: Device Organization for Eight-Die Package (BGA/LGA) ................................................................... 26 Figure 18: Array Organization per Logical Unit (LUN) ..................................................................................... 27 Figure 19: Asynchronous Command Latch Cycle ............................................................................................ 29 Figure 20: Asynchronous Address Latch Cycle ................................................................................................ 30 Figure 21: Asynchronous Data Input Cycles ................................................................................................... 31 Figure 22: Asynchronous Data Output Cycles ................................................................................................. 32 Figure 23: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 33 Figure 24: READ/BUSY# Open Drain ............................................................................................................. 34 Figure 25: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 35 Figure 26: tFall and tRise (VCCQ = 1.7-1.95V) .................................................................................................... 35 Figure 27: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 36 Figure 28: IOL vs Rp (VCCQ = 1.7-1.95V) .......................................................................................................... 36 Figure 29: TC vs Rp ........................................................................................................................................ 37 Figure 30: Synchronous Bus Idle/Driving Behavior ......................................................................................... 40 Figure 31: Synchronous Command Cycle ....................................................................................................... 41 Figure 32: Synchronous Address Cycle ........................................................................................................... 42 Figure 33: Synchronous DDR Data Input Cycles ............................................................................................. 43 Figure 34: Synchronous DDR Data Output Cycles ........................................................................................... 45 Figure 35: R/B# Power-On Behavior ............................................................................................................... 46 Figure 36: Activating the Synchronous Interface ............................................................................................. 48 Figure 37: RESET (FFh) Operation ................................................................................................................. 51 Figure 38: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 52 Figure 39: READ ID (90h) with 00h Address Operation .................................................................................... 53 Figure 40: READ ID (90h) with 20h Address Operation .................................................................................... 53 Figure 41: SET FEATURES (EFh) Operation .................................................................................................... 56 Figure 42: GET FEATURES (EEh) Operation ................................................................................................... 56 Figure 43: READ PARAMETER (ECh) Operation .............................................................................................. 60 Figure 44: READ UNIQUE ID (EDh) Operation ............................................................................................... 70 Figure 45: READ STATUS (70h) Operation ...................................................................................................... 73 www..com Figure 46: READ STATUS ENHANCED (78h) Operation .................................................................................. 73 Figure 47: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 74 Figure 48: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation ......................................................... 75 Figure 49: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 76 Figure 50: CHANGE ROW ADDRESS (85h) Operation ..................................................................................... 78
List of Figures
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Figure 51: READ PAGE (00h-30h) Operation ................................................................................................... 82 Figure 52: READ PAGE CACHE SEQUENTIAL (31h) Operation ........................................................................ 83 Figure 53: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 85 Figure 54: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 86 Figure 55: READ PAGE MULTI-PLANE (00h-32h) Operation ........................................................................... 88 Figure 56: PROGRAM PAGE (80h-10h) Operation ........................................................................................... 90 Figure 57: PROGRAM PAGE CACHE (80h-15h) Operation (Start) .................................................................... 92 Figure 58: PROGRAM PAGE CACHE (80h-15h) Operation (End) ..................................................................... 92 Figure 59: PROGRAM PAGE MULTI-PLANE (80h-11h) Operation ................................................................... 94 Figure 60: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 95 Figure 61: ERASE BLOCK MULTI-PLANE (60h-D1h) Operation ...................................................................... 96 Figure 62: COPYBACK READ (00h-35h) Operation .......................................................................................... 98 Figure 63: COPYBACK READ (00h-35h) with CHANGE READ COLUMN (05h-E0h) Operation .......................... 98 Figure 64: COPYBACK PROGRAM (85h-10h) Operation .................................................................................. 99 Figure 65: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation ........................ 99 Figure 66: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation .......................................................... 100 Figure 67: PROGRAM OTP PAGE (80h-10h) Operation ................................................................................... 102 Figure 68: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation ......................... 103 Figure 69: PROTECT OTP AREA (80h-10h) Operation .................................................................................... 104 Figure 70: READ OTP PAGE (00h-30h) Operation .......................................................................................... 104 Figure 71: Overshoot .................................................................................................................................... 111 Figure 72: Undershoot ................................................................................................................................. 111 Figure 73: RESET Operation ......................................................................................................................... 124 Figure 74: READ STATUS Cycle ..................................................................................................................... 124 Figure 75: READ STATUS ENHANCED Cycle ................................................................................................. 125 Figure 76: READ PARAMETER PAGE ............................................................................................................. 126 Figure 77: READ PAGE ................................................................................................................................. 126 Figure 78: READ PAGE Operation with CE# "Don't Care" ............................................................................... 127 Figure 79: CHANGE READ COLUMN ............................................................................................................ 128 Figure 80: READ PAGE CACHE SEQUENTIAL ................................................................................................ 129 Figure 81: READ PAGE CACHE RANDOM ..................................................................................................... 130 Figure 82: READ ID Operation ...................................................................................................................... 131 Figure 83: PROGRAM PAGE Operation .......................................................................................................... 131 Figure 84: PROGRAM PAGE Operation with CE# "Don't Care" ....................................................................... 132 Figure 85: PROGRAM PAGE Operation with CHANGE WRITE COLUMN ........................................................ 132 Figure 86: PROGRAM PAGE CACHE .............................................................................................................. 133 Figure 87: PROGRAM PAGE CACHE Ending on 15h ....................................................................................... 133 Figure 88: COPYBACK .................................................................................................................................. 134 Figure 89: ERASE BLOCK Operation .............................................................................................................. 134 Figure 90: SET FEATURES Operation ............................................................................................................ 135 Figure 91: READ ID Operation ...................................................................................................................... 136 Figure 92: GET FEATURES Operation ........................................................................................................... 137 Figure 93: RESET (FCh) Operation ................................................................................................................ 138 Figure 94: READ STATUS Cycle ..................................................................................................................... 139 Figure 95: READ STATUS ENHANCED Operation .......................................................................................... 140 Figure 96: READ PARAMETER PAGE Operation ............................................................................................. 141 www..com Figure 97: READ PAGE Operation ................................................................................................................. 142 Figure 98: CHANGE READ COLUMN ............................................................................................................ 143 Figure 99: READ PAGE CACHE SEQUENTIAL (1 of 2) ..................................................................................... 144 Figure 100: READ PAGE CACHE SEQUENTIAL (2 of 2) ................................................................................... 145 Figure 101: READ PAGE CACHE RANDOM (1 of 2) ......................................................................................... 146 Figure 102: READ PAGE CACHE RANDOM (2 of 2) ......................................................................................... 146
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Figure 113: Figure 114: Figure 115: Figure 116: Multi-Plane Read Page (1 of 2) ..................................................................................................... 147 Multi-Plane Read Page (2 of 2) ..................................................................................................... 148 PROGRAM PAGE Operation (1 of 2) ............................................................................................. 149 PROGRAM PAGE Operation (2 of 2) ............................................................................................. 149 CHANGE WRITE COLUMN ......................................................................................................... 150 Multi-Plane Program Page .......................................................................................................... 151 ERASE BLOCK ............................................................................................................................ 152 COPYBACK (1 of 3) ..................................................................................................................... 152 COPYBACK (2 of 3) ..................................................................................................................... 153 COPYBACK (3 of 3) ..................................................................................................................... 153 READ OTP PAGE ........................................................................................................................ 154 PROGRAM OTP PAGE (1 of 2) ...................................................................................................... 155 PROGRAM OTP PAGE (2 of 2) ...................................................................................................... 155 PROTECT OTP AREA .................................................................................................................. 156
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND General Description
General Description
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands,address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#). This Micron NAND Flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe (DQS). This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). For further details, see Device and Array Organization.
Asynchronous and Synchronous Signal Descriptions
Table 1: Asynchronous and Synchronous Signal Definitions
Asynchronous Signal1 ALE CE# CLE DQx - RE# Synchronous Signal1 ALE CE# CLE DQx DQS W/R# Type Input Input Input I/O I/O Input Description2 Address latch enable: Loads an address from DQx into the address register. Chip enable: Enables or disables one or more die (LUNs) in a target1. Command latch enable: Loads a command from DQx into the command register. Data inputs/outputs: The bidirectional I/Os transfer address, data, and command information. Data strobe: Provides a synchronous reference for data input and output. Read enable and write/read: RE# transfers serial data from the NAND Flash to the host system when the asynchronous interface is active. When the synchronous interface is active, W/R# controls the direction of DQx and DQS. Write enable and clock: WE# transfers commands, addresses, and serial data from the host system to the NAND Flash when the asynchronous interface is active. When the synchronous interface is active, CLK latches command and address cycles. Write protect: Enables or disables array PROGRAM and ERASE operations. Ready/busy: An open-drain, active-low output that requires an external pull-up resistor. This signal indicates target array activity. VCC: Core power supply
WE#
CLK
Input
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R/B# VCC
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WP# R/B# VCC
Input Output Supply
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Asynchronous and Synchronous Signal Descriptions
Table 1: Asynchronous and Synchronous Signal Definitions (Continued)
Asynchronous Signal1 VCCQ VSS VSSQ NC DNU RFU Synchronous Signal1 VCCQ VSS VSSQ NC DNU RFU Notes: Type Supply Supply Supply - - - Description2 VCCQ: I/O power supply VSS: Core ground connection VSSQ: I/O ground connection No connect: NCs are not internally connected. They can be driven or left unconnected. Do not use: DNUs must be left unconnected. Reserved for future use: RFUs must be left unconnected.
1. See Device and Array Organization for detailed signal connections. 2. See Bus Operation - Asynchronous Interface (page 28) and Bus Operation - Synchronous Interface (page 38) for detailed asynchronous and synchronous interface signal descriptions.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync x8
NC NC NC NC NC R/B2#1 R/B# W/R# CE# CE2#1 NC VCC VSS NC NC CLE ALE CLK WP# NC NC NC NC NC
Async x8
NC NC NC NC NC R/B2#1 R/B# RE# CE# CE2#1 NC VCC VSS NC NC CLE ALE WE# WP# NC NC NC NC NC 1l 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Async x8
DNU/VSSQ2 NC NC NC DQ7 DQ6 DQ5 DQ4 NC DNU/VCCQ2 DNU VCC VSS DNU DNU/VCCQ2 NC DQ3 DQ2 DQ1 DQ0 NC NC DNU DNU/VSSQ2
Sync x8
DNU/VSSQ2 NC NC NC DQ7 DQ6 DQ5 DQ4 NC DNU/VCCQ2 DNU VCC VSS DQS DNU/VCCQ2 NC DQ3 DQ2 DQ1 DQ0 NC NC DNU DNU/VSSQ2
Notes:
1. CE2# and R/B2# are available on dual die and quad die packages. They are NC for other configurations. 2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.1. If not supplying VCCQ or VSSQ to these pins, do not use them. 3. TSOP devices do not support the synchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Signal Assignments
Figure 3: 52-Pad LGA (Top View)
0 1 2 3 4 5 6 7 8
NC
OA
2 CE4#
2 R/B4#
A
2 CE3#
CLE-1
CE#
2 R/B3#
B OB NC C ALE-1
VSS CLE-21 CE2#1
VCC NC RE#-1
D OC DNU E WE#-21
ALE-21
RE#-21 DNU WE#-1 R/B# R/B2#1
F DQ0-21
WP#-1
VSS DQ0-1 WP#-21 DQ7-21
G
H
DQ1-1
DQ7-1
J OD DNU/ VSS
DQ1-21
DQ2-1
DQ6-1
DQ6-21 DNU
K
DQ3-1
DQ5-1 DQ5-21 DNU/ VSS
L OE NC M
DQ2-21
VSS VSS
DQ4-1
VCC DQ3-21 DQ4-21 DNU/ VCC
N OF NC
DNU/ VCC
NC
Top View, Pads Down
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Notes:
1. These signals are available on quad and octal die packages. They are NC for other configurations. 2. These signals are available on quad die four CE# or octal die packages. They are NC for other configurations.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Signal Assignments
Figure 4: 100-Ball BGA (Ball-Down, Top View)
1 2 3 4 5 6 7 8 9 10
A
NC
NC
NC
NC
A
B
NC
NC
B
D
RFU
DNU
NC
3 WP#-2
NC
NC
DNU
RFU
D
E
RFU
DNU
NC
WP#-1
NC
NC
DNU
RFU
E
F
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F
G
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G
H
Vssq
Vccq
RFU
RFU
R/B2#3
R/B4#4
Vccq
Vssq
H
J
3 DQ0-2
3 DQ2-2
3 ALE-2
CE4#4
R/B#
R/B3#4
3 DQ5-2
3 DQ7-2
J
K
DQ0-1
DQ2-1
ALE-1
CE3#4
CE2#3
CE#
DQ5-1
DQ7-1
K
L
Vccq
Vssq
Vccq
CLE-23
3 RE#-2 (W/R#-2)
Vccq
Vssq
Vccq
L
M
3 DQ1-2
3 DQ3-2
Vssq
CLE-1
RE#-1 (W/R#-1) RFU
Vssq
3 DQ4-2
3 DQ6-2
M
N
DQ1-1
DQ3-1
RFU
N/A1 (DQS-23) N/A1 (DQS-1)
3 WE#-2 (CLK-2)
DQ4-1
DQ6-1
N
P
Vssq
Vccq
RFU
RFU
WE#-1 (CLK-1)
Vccq
Vssq
P
T
NC
NC
T
U
NC
NC
NC
NC
U
1
2
3
4
5
6
7
8
9
10
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1. N/A: This signal is tri-stated when the asynchronous interface is active. 2. Signal names in parentheses are the signal names when the synchronous interface is active. 3. These signals are available on dual, quad, and octal die packages. They are NC for other configurations. 4. These signals are available on quad die four CE# or octal die packages. They are NC for other configurations.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Package Dimensions
Package Dimensions
Figure 5: 48-Pin TSOP - Type 1 CPL (Package Code: WP)
0.25 for reference only 0.50 TYP for reference only Mold compound: Epoxy novolac Plated lead finish: 100% Sn Package width and length do not include mold protrusion. Allowable protrusion is 0.25 per side.
20.00 0.25 18.40 0.08 1 48
12.00 0.08
0.27 MAX 0.17 MIN
24
25
0.25 0.10 0.15 +0.03 -0.02 See detail A 1.20 MAX 0.10 +0.10 -0.05 Gage plane
0.50 0.1 0.80
Detail A
Note:
1. All dimensions are in millimeters.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Package Dimensions
Figure 6: 52-Pad VLGA
Seating plane 0.1 A See Detail B Section A-A
A
See Note 1 Detail B2 Not to scale Substrate material: plastic laminate. Mold compound: epoxy novolac.
40X O0.71 12X O11
8 7 6 5
6 CTR 4 CTR
4 3 2 1 0
Terminal A1 ID
Terminal A1 ID
OA
A B C D E F G
OB
OC
13 12 10 CTR CTR CTR
A 2 TYP
A
18 0.1
H OD J K L M N
OE
OF
2 TYP
2 TYP 10 CTR 14 0.1
1.0 MAX including package bow.
Bottom side saw fiducials may or may not be covered with soldermask.
Notes: 1. Pads are nonsolder mask defined (NSMD) and are plated with 3-15 microns of nickel followed by a minimum of 0.1 microns of soft wire bondable gold (99.99% pure). 2. Primary datum A (seating plane) is defined by the bottom terminal surface. Terminals need not extend below the package bottom surface.
Note:
1. All dimensions are in millimeters.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Package Dimensions
Figure 7: 100-Ball VBGA - 12mm x 18mm (Package Code: H1)
Seating plane 0.12 A A 0.63 0.05
100X O0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post-reflow on O0.4 SMD ball pads.
12 0.1 Ball A1 ID
A B
10
9
8
7
6
5
4
3
2
1
Ball A1 ID
D
8
E
7
F G H
16 CTR
J K L M N
18 0.1
1 TYP
P
T U
1 TYP 1 TYP 9 CTR
1.0 MAX Bottom side 0.25 MIN saw fiducials may or may not be covered with soldermask.
Note:
1. All dimensions are in millimeters.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Package Dimensions
Figure 8: 100-Ball TBGA - 12mm x 18mm (Package Code: H2)
Seating plane 0.12 A 100X O0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post-reflow on O0.4 SMD ball pads. A 0.73 0.05
12 0.1
10 9 8 7 6 5 4 3 2 1 A B
Ball A1 ID
Ball A1 ID
D
8
E
7
F G H
16 CTR
J K L M N
18 0.1
1 TYP
P
T U
Bottom side fiducials may or may not be covered with soldermask.
1 TYP 1 TYP 9 CTR
1.2 MAX 0.25 MIN
Note:
1. All dimensions are in millimeters.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Package Dimensions
Figure 9: 100-Ball LBGA - 12mm x 18mm (Package Code: H3)
Seating plane 0.12 A A 0.98 0.05
100X O0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls postreflow on O0.40 SMD ball pads.
12 0.1
10 9 8 7 6 5 4 3 2 1 A B
Ball A1 ID
Ball A1 ID
D E F G H
16 CTR 10 CTR
J K L M N P
18 0.1
1 TYP
T U
1 TYP 9 CTR
1.4 MAX Bottom side 0.25 MIN saw fiducials may or may not be covered with soldermask.
Note:
1. All dimensions are in millimeters.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. The addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address. Data is transferred to or from the NAND Flash memory array, byte by byte, through a data register and a cache register. The NAND Flash memory array is programmed and read using page-based operations and is erased using block-based operations. During normal page operations, the data and cache registers act as a single register. During cache operations, the data and cache registers operate independently to increase data throughput. The status register reports the status of die (LUN) operations. Figure 10: NAND Flash Die (LUN) Functional Block Diagram
Vcc Vss Vccq Vssq
Async
Sync
I/O control Address register Status register
DQ[7:0] DQ[7:0]
N/A DQS
Command register
CE# CLE ALE WE# RE# WP#
CE# CLE CLK W/R# WP# Row Decode Row Decode ALE Control logic
Column Decode Column decode
NAND Flash NAND Flash array Array (2 planes)
R/B#
R/B#
Data Register Data register Cache Register Cache register
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Notes: 1. N/A: This signal is tri-stated when the asynchronous interface is active. 2. Some devices do not include the synchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Device and Array Organization
Device and Array Organization
Figure 11: Device Organization for Single-Die Package (TSOP/BGA)
Async CE# CLE ALE WE# RE# N/A WP#
Sync CE# CLE ALE CLK W/R# DQS WP#
Package Target 1 LUN 1
R/B#
DQ[7:0] DQ[7:0]
Note:
1. TSOP devices do not support the synchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Device and Array Organization
Figure 12: Device Organization for Two-Die Package (TSOP)
Async CE# CLE ALE WE# RE# DQ[7:0] N/A WP# Sync CE# CLE ALE CLK W/R# DQ[7:0] DQS WP# Package Target 1 LUN 1
R/B#
CE2# CLE ALE WE# RE# DQ[7:0] N/A WP#
CE2# CLE ALE CLK W/R# DQ[7:0] DQS WP#
Target 2 LUN 1
R/B2#
Note:
1. TSOP devices do not support the synchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Device and Array Organization
Figure 13: Device Organization for Two-Die Package (BGA)
Package Target 1 LUN 1
Async CE# CLE-1 ALE-1 WE#-1 RE#-1 DQ[7:0]-1 N/A WP#-1
Sync CE# CLE-1 ALE-1 CLK-1 W/R#-1 DQ[7:0]-1 DQS-1 WP#-1
R/B#
CE2# CLE-2 ALE-2 WE#-2 RE#-2 DQ[7:0]-2 N/A WP#-2
CE2# CLE-2 ALE-2 CLK-2 W/R#-2 DQ[7:0]-2 DQS-2 WP#-2
Target 2 LUN 1
R/B2#
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Device and Array Organization
Figure 14: Device Organization for Four-Die Package (TSOP)
Async CE# CLE ALE WE# RE# DQ[7:0] N/A WP# Sync CE# CLE ALE CLK W/R# DQ[7:0] DQS WP# Package Target 1 LUN 1 LUN 2
R/B#
CE2# CLE ALE WE# RE# DQ[7:0] N/A WP#
CE2# CLE ALE CLK W/R# DQ[7:0] DQS WP#
Target 2 LUN 1 LUN 2
R/B2#
Note:
1. TSOP devices do not support the synchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Device and Array Organization
Figure 15: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA)
Async CE# CLE-1 ALE-1 WE#-1 RE#-1 DQ[7:0]-1 N/A WP#-1
Sync CE# CLE-1 ALE-1 CLK-1 W/R#-1 DQ[7:0]-1 DQS-1 WP#-1
Package Target 1 LUN 1 LUN 2
R/B#
CE2# CLE-2 ALE-2 WE#-2 RE#-2 DQ[7:0]-2 N/A WP#-2
CE2# CLE-2 ALE-2 CLK-2 W/R#-2 DQ[7:0]-2 DQS-2 WP#-2
Target 2 LUN 1 LUN 2
R/B2#
Note:
1. LGA devices do not support the synchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Device and Array Organization
Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA)
Package Target 1 LUN 1
Async CE# CLE-1 ALE-1 WE#-1 RE#-1 N/A WP#-1 CE2# CLE-2 ALE-2 WE#-2 RE#-2 N/A WP#-2 CE3# CLE-1 ALE-1 WE#-1 RE#-1 N/A WP#-1 CE4# CLE-2 ALE-2 WE#-2 RE#-2 N/A WP#-2
Sync CE# CLE-1 ALE-1 CLK-1 W/R#-1 DQS-1 WP#-1 CE2# CLE-2 ALE-2 CLK-2 W/R#-2 DQS-2 WP#-2 CE3# CLE-1 ALE-1 CLK-1 W/R#-1 DQS-1 WP#-1 CE4# CLE-2 ALE-2 CLK-2 W/R#-2 DQS-2 WP#-2
R/B#
DQ[7:0]-1 DQ[7:0]-1
Target 2 LUN 1
R/B2#
DQ[7:0]-2 DQ[7:0]-2
Target 3 LUN 1
R/B3#
DQ[7:0]-1 DQ[7:0]-1
Target 4 LUN 1
R/B4#
DQ[7:0]-2 DQ[7:0]-2
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Note:
1. LGA devices do not support the synchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Device and Array Organization
Figure 17: Device Organization for Eight-Die Package (BGA/LGA)
Package Target 1 LUN 1 LUN 2
Async CE# CLE-1 ALE-1 WE#-1 RE#-1 N/A WP#-1 CE2# CLE-2 ALE-2 WE#-2 RE#-2 N/A WP#-2 CE3# CLE-1 ALE-1 WE#-1 RE#-1 N/A WP#-1 CE4# CLE-2 ALE-2 WE#-2 RE#-2 N/A WP#-2
Sync CE# CLE-1 ALE-1 CLK-1 W/R#-1 DQS-1 WP#-1 CE2# CLE-2 ALE-2 CLK-2 W/R#-2 DQS-2 WP#-2 CE3# CLE-1 ALE-1 CLK-1 W/R#-1 DQS-1 WP#-1 CE4# CLE-2 ALE-2 CLK-2 W/R#-2 DQS-2 WP#-2
R/B#
DQ[7:0]-1 DQ[7:0]-1
Target 2 LUN 1 LUN 2
R/B2#
DQ[7:0]-2 DQ[7:0]-2
Target 3 LUN 1 LUN 2
R/B3#
DQ[7:0]-1 DQ[7:0]-1
Target 4 LUN 1 LUN 2
R/B4#
DQ[7:0]-2 DQ[7:0]-2
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Note:
1. LGA devices do not support the synchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Device and Array Organization
Figure 18: Array Organization per Logical Unit (LUN)
Logical Unit (LUN)
4320 bytes
Cache Registers Data Registers
4320 bytes
DQ7
4096 4096
224 224
4096 4096
224 224
DQ0
1 page = (4K + 224 bytes)
2048 blocks per plane 4096 blocks per LUN
1 Block
1 Block
1 block = (4K + 224) bytes x 128 pages = (512K + 28K) bytes
1 Block
1 plane = (512K + 28K) bytes x 2048 blocks = 8640Mb 1 LUN = 8640Mb x 2 planes = 17,280Mb
Plane 0 (0, 2, 4, ..., 4094)
Plane 1 (1, 3, 5, ..., 4095)
Table 2: Array Addressing for Logical Unit (LUN)
Cycle First Second Third Fourth Fifth DQ7 CA7 LOW BA74 BA15 LOW Notes: DQ6 CA6 LOW PA6 BA14 LOW DQ5 CA5 LOW PA5 BA13 LOW DQ4 CA4 CA123 PA4 BA12 LOW DQ3 CA3 CA11 PA3 BA11 LA05 DQ2 CA2 CA10 PA2 BA10 BA18 DQ1 CA1 CA9 PA1 BA9 BA17 DQ0 CA02 CA8 PA0 BA8 BA16
1. CAx = column address, PAx = page address, BAx = block address, LAx = LUN address; the page address, block address, and LUN address are collectively called the row address. 2. When using the synchronous interface, CA0 is forced to 0 internally; one data cycle always returns one even byte and one odd byte. 3. Column addresses 4320 (10E0h) through 8191 (1FFFh) are invalid, out of bounds, do not exist in the device, and cannot be addressed. 4. BA[7] is the plane-select bit: Plane 0: BA[7] = 0 Plane 1: BA[7] = 1 5. LA0 is the LUN-select bit. It is present only when two LUNs are shared on the target; otherwise, it should be held LOW. LUN 0: LA0 = 0 LUN 1: LA0 = 1
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Bus Operation - Asynchronous Interface
Bus Operation - Asynchronous Interface
The asynchronous interface is active when the NAND Flash device powers on. The I/O bus, DQ[7:0], is multiplexed sharing data I/O, addresses, and commands. The DQS signal, if present, is tri-stated when the asynchronous interface is active. Asynchronous interface bus modes are summarized below. Table 3: Asynchronous Interface Mode Selection
Mode Standby Bus idle Command input Address input Data input Data output Write protect Notes: CE# H L L L L L X CLE X X H L L L X ALE X X L H L L X H X X WE# X H RE# X H H H H DQS X X X X X X X DQx X X input input input output X WP# 0V/VCCQ X H H H X L
2
Notes 2
1. DQS is tri-stated when the asynchronous interface is active. 2. WP# should be biased to CMOS LOW or HIGH for standby. 3. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL.
Asynchronous Enable/Standby
A chip enable (CE#) signal is used to enable or disable a target. When CE# is driven LOW, all of the signals for that target are enabled. With CE# LOW, the target can accept commands, addresses, and data I/O. There may be more than one target in a NAND Flash package. Each target is controlled by its own chip enable; the first target (Target 0) is controlled by CE#; the second target (if present) is controlled by CE2#, etc. A target is disabled when CE# is driven HIGH, even when the target is busy. When disabled, all of the target's signals are disabled except CE#, WP#, and R/B#. This functionality is also known as CE# "Don't Care". While the target is disabled, other devices can utilize the disabled NAND signals that are shared with the NAND Flash. A target enters low-power standby when it is disabled and is not busy. If the target is busy when it is disabled, the target enters standby after all of the die (LUNs) complete their operations. Standby helps reduce power consumption.
Asynchronous Bus Idle
A target's bus is idle when CE# is LOW, WE# is HIGH, and RE# is HIGH.
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During bus idle, all of the signals are enabled except DQS, which is not used when the asynchronous interface is active. No commands, addresses, and data are latched into the target; no data is output.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Bus Operation - Asynchronous Interface Asynchronous Commands
An asynchronous command is written from DQ[7:0] to the command register on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH. Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are accepted by die (LUNs) even when they are busy. Figure 19: Asynchronous Command Latch Cycle
CLE
tCLS tCS tCLH tCH
CE#
tWP
WE#
tALS tALH
ALE
tDS tDH
DQx
COMMAND
Don't Care
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Bus Operation - Asynchronous Interface Asynchronous Addresses
An asynchronous address is written from DQ[7:0] to the address register on the rising edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH. Bits that are not part of the address space must be LOW (see Device and Array Organization). The number of cycles required for each command varies. Refer to the command descriptions to determine addressing requirements (see Command Definitions). Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some addresses are accepted by die (LUNs) even when they are busy; for example, address cycles that follow the READ STATUS ENHANCED (78h) command. Figure 20: Asynchronous Address Latch Cycle
CLE
tCLS tCS
CE#
tWP
WE#
tWC
tWH
tALS
tALH
ALE
tDS tDH
DQx
Col add 1
Col add 2
Row add 1
Row add 2 Don't Care
Row add 3 Undefined
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Bus Operation - Asynchronous Interface Asynchronous Data Input
Data is written from DQ[7:0] to the cache register of the selected die (LUN) on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH. Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Figure 21: Asynchronous Data Input Cycles
CLE tCLH
CE# tALS ALE tWP WE# tWH tDS tDH DQx
Din M
tCH
tWC
tWP
tWP
tDS tDH
Din M+1
tDS tDH
Din N
Don't Care
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Bus Operation - Asynchronous Interface Asynchronous Data Output
Data can be output from a die (LUN) if it is in a READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the selected die (LUN) to DQ[7:0] on the falling edge of RE# when CE# is LOW, ALE is LOW, CLE is LOW, and WE# is HIGH. If the host controller is using a tRC of 30ns or greater, the host can latch the data on the rising edge of RE# (see Figure 22 for proper timing). If the host controller is using a tRC of less than 30ns, the host can latch the data on the next falling edge of RE# (see Figure 23 (page 33) for extended data output (EDO) timing). Using the READ STATUS ENHANCED (78h) command prevents data contention following an interleaved die (multi-LUN) operation. After issuing the READ STATUS ENHANCED (78h) command, to enable data output, issue the READ MODE (00h) command. Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); however, it is possible to output data from the status register even when a die (LUN) is busy by first issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command. Figure 22: Asynchronous Data Output Cycles
tCEA
CE#
tREA tRP tREH tREA tREA tCOH tCHZ
RE#
tRHZ tRHZ tRHOH
DQx
tRR
Dout
tRC
Dout
Dout
RDY Don't Care
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Figure 23: Asynchronous Data Output Cycles (EDO Mode)
CE# tRC tRP RE# tREA tCEA DQx tREA tRLOH Dout Dout tRHZ tRHOH Dout tREH tCHZ tCOH
tRR RDY Don't Care
Write Protect
The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When WP# is HIGH, PROGRAM and ERASE operations are enabled. It is recommended that the host drive WP# LOW during power-on until Vcc and Vccq are stable to prevent inadvertent PROGRAM and ERASE operations (see Device Initialization (page 46) for additional details). WP# must be transitioned only when the target is not busy and prior to beginning a command sequence. After a command sequence is complete and the target is ready, WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issuing a new command. The WP# signal is always an active input, even when CE# is HIGH. This signal should not be multiplexed with other signals.
Ready/Busy#
The ready/busy# (R/B#) signal provides a hardware method of indicating whether a target is ready or busy. A target is busy when one or more of its die (LUNs) are busy (RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each die (LUN) contains a status register, it is possible to determine the independent status of each die (LUN) by polling its status register instead of using the R/B# signal (see Status Operations (page 71) for details regarding die (LUN) status). This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the target is ready, and transitions LOW when the target is busy. The signal's open-drain
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driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an interrupt pin on the system controller (see Figure 24 (page 34)). The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# signal. The actual value used for Rp depends on the system timing requirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10to 90-percent points on the R/B# waveform, the rise time is approximately two time constants (TC).
TC = R x C Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the R/B# signal and the total load capacitance. Approximate Rp values using a circuit load of 100pF are provided in Figure 29 (page 37). The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and Vccq.
Vcc (MAX) - Vol (MAX) IOL + il Where il is the sum of the input currents of all devices tied to the R/B# pin. Rp =
Figure 24: READ/BUSY# Open Drain
Vccq
Vcc
Rp
To controller R/B# Open drain output
IOL
Vss Device
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Figure 25: tFall and tRise (VCCQ = 2.7-3.6V)
3.50 3.00 2.50 V 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 TC
Notes:
tFall tRise
2
4
6
Vccq 3.3V
1. tFALL is VOH(DC) to VOL(AC) and tRISE is VOL(DC) to VOH(AC). 2. tRise dependent on external capacitance and resistive loading and output transistor impedance. 3. tRise primarily dependent on external pull-up resistor and external capacitive loading. 4. tFall = 10ns at 3.3V 5. See TC values in Figure 29 (page 37) for approximate Rp value and TC.
Figure 26: tFall and tRise (VCCQ = 1.7-1.95V)
3.50 3.00 2.50 V 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 TC 0 2 4 6
Vccq 1.8V
tFall
tRise
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Notes:
1. 2. 3. 4.
is VOH(DC) to VOL(AC) and tRISE is VOL(DC) to VOH(AC). is primarily dependent on external pull-up resistor and external capacitive loading. tFall 7ns at 1.8V. See TC values in Figure 29 (page 37) for TC and approximate Rp value.
tRise
tFALL
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Figure 27: IOL vs Rp (VCCQ = 2.7-3.6V)
3.50 3.00 2.50 2.00 I (mA) 1.50 1.00 0.50 0.00 0 2000 400 0 6000 Rp ()
IOL at Vccq (MAX)
8000
10,000
12,000
Figure 28: IOL vs Rp (VCCQ = 1.7-1.95V)
3.50 3.00 2.50 2.00
I (mA)
1.50 1.00 0.50 0.00 0 2000 4000 6000 8000 10,000 12,000
Rp () IOL at Vccq (MAX)
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Figure 29: TC vs Rp
1200 1000 800
T(ns)
600 400 200 0 0 2000 4000 6000 8000 10,000 12,000
Rp ()
Iol at Vccq (MAX) RC = TC C = 100pF
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Bus Operation - Synchronous Interface
Bus Operation - Synchronous Interface
These NAND Flash devices have two interfaces--a synchronous interface for fast data I/O transfer and an asynchronous interface that is backward compatible with existing NAND Flash devices. The NAND Flash command protocol for both the asynchronous and synchronous interfaces is identical. However, there are some differences betweeen the asynchronous and synchronous interfaces when issuing command, address, and data I/O cycles using the NAND Flash signals. When the synchronous interface is activated on a target (see Activating Interfaces (page 47)), the target is capable of high-speed DDR data transfers. Existing signals are redefined for high-speed DDR I/O. The WE# signal becomes CLK. DQS is enabled. The RE# signal becomes W/R#. CLK provides a clock reference to the NAND Flash device. DQS is a bidirectional data strobe. During data output, DQS is driven by the NAND Flash device. During data input, DQS is controlled by the host controller while inputting data on DQ[7:0]. The direction of DQS and DQ[7:0] is controlled by the W/R# signal. When the W/R# signal is latched HIGH, the controller is driving the DQ bus and DQS. When the W/R# is latched LOW, the NAND Flash is driving the DQ bus and DQS. The synchronous interface bus modes are summarized below. Table 4: Synchronous Interface Mode Selection
Mode Standby Bus idle Bus driving Command input Address input Data input Data output Write protect Undefined CE# H L L L L L L X L CLE X L L H L H H X L H Notes: 1. 2. 3. 4. ALE X L L L H H H X H L X CLK X W/R# X H L H H H L X L L See Note 5 X output output DQS X X output X X DQ[7:0] X X output input input input output X output output WP# 0V/VCCQ X X H H H X L X X 3 3 4 5 Notes 1, 2
Undefined L www..com
CLK can be stopped when the target is disabled, even when R/B# is LOW. WP# should be biased to CMOS LOW or HIGH for standby. Commands and addresses are latched on the rising edge of CLK. During data input to the device, DQS is the "clock" that latches the data in the cache register.
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5. During data output from the NAND Flash device, DQS is an output generated from CLK after tDQSCK delay. 6. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL.
Synchronous Enable/Standby
In addition to the description in the section Asynchronous Enable/Standby (page 28), the following requirements also apply when the synchronous interface is active. Before enabling a target, CLK must be running and ALE and CLE must be LOW. When CE# is driven LOW, all of the signals for the selected target are enabled. The target is not enabled until tCS completes; the target's bus is then idle. Prior to disabling a target, the target's bus must be idle. A target is disabled when CE# is driven HIGH, even when it is busy. All of the target's signals are disabled except CE#, WP#, and R/B#. After the target is disabled, CLK can be stopped. A target enters low-power standby when it is disabled and is not busy. If the target is busy when it is disabled, the target enters standby after all of the die (LUNs) complete their operations.
Synchronous Bus Idle/Driving
A target's bus is idle or driving when CLK is running, CE# is LOW, ALE is LOW, and CLE is LOW. The bus is idle when W/R# transitions HIGH and is latched by CLK. During the bus idle mode, all signals are enabled; DQS and DQ[7:0] are inputs. No commands, addresses, or data are latched into the target; no data is output. When entering the bus idle mode, the host must wait a minimum of tCAD before changing the bus mode. In the bus idle mode, the only valid bus modes supported are: bus driving, command, address, and DDR data input. The bus is driving when W/R# transitions LOW and is latched by CLK. During the bus driving mode, all signals are enabled; DQS is LOW and DQ[7:0] is driven LOW or HIGH, but no valid data is output. Following the bus driving mode, the only valid bus modes supported are bus idle and DDR data output.
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Figure 30: Synchronous Bus Idle/Driving Behavior
CE#
CLE
ALE
CLK
tCALS tCALS
W/R#
tDQSD tDQSHZ
DQS
DQ[7:0]
Bus idle
Bus driving
Bus idle Undefined (driven by NAND)
Note:
1. Only the selected die (LUN) drives DQS and DQ[7:0]. During an interleaved die (multiLUN) operation, the host must use the READ STATUS ENHANCED (78h) to prevent data output contention.
Synchronous Commands
A command is written from DQ[7:0] to the command register on the rising edge of CLK when CE# is LOW, ALE is LOW, CLE is HIGH, and W/R# is HIGH. After a command is latched--and prior to issuing the next command, address, or data I/O--the bus must go to bus idle mode on the next rising edge of CLK, except when the clock period, tCK, is greater than tCAD. Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some commands, such as READ STATUS (70h) and READ STATUS ENHANCED (78h), are accepted by die (LUNs), even when they are busy.
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Figure 31: Synchronous Command Cycle
tCS
tCH
CE#
tCALS tCALS tCALH
CLE
tCALS tCAD
tCALS
tCALH
tCALH
ALE
tCKL tCKH
CLK
tCK tCAD starts here1 tCALH tDQSHZ
W/R#
tCALS
DQS
tCAS tCAH
DQ[7:0]
COMMAND
Undefined
Don't Care
Note:
1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the command cycle is latched for subsequent command, address, data input, or data output cycle(s).
Synchronous Addresses
A synchronous address is written from DQ[7:0] to the address register on the rising edge of CLK when CE# is LOW, ALE is HIGH, CLE is LOW, and W/R# is HIGH. After an address is latched--and prior to issuing the next command, address, or data I/O --the bus must go to bus idle mode on the next rising edge of CLK, except when the clock period, tCK, is greater than tCAD. Bits not part of the address space must be LOW (see Device and Array Organization). The number of address cycles required for each command varies. Refer to the command descriptions to determine addressing requirements. Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some addresses such as address cycles that follow the READ STATUS ENHANCED (78h) command, are accepted by die (LUNs), even when they are busy.
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Figure 32: Synchronous Address Cycle
tCS
tCH
CE#
tCALS tCALH tCAD tCALS tCKL tCKH tCALH
CLE
tCALS tCALS tCALH
ALE
CLK
tCK tCAD starts here1 tCALH tDQSHZ
W/R#
tCALS
DQS
tCAS tCAH
DQ[7:0]
ADDRESS
Undefined
Don't Care
Note:
1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the command cycle is latched for subsequent command, address, data input, or data output cycle(s).
Synchronous DDR Data Input
To enter the DDR data input mode, the following conditions must be met: * * * * * * CLK is running CE# is LOW W/R# is HIGH tCAD is met DQS is LOW ALE and CLE are HIGH on the rising edge of CLK
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Upon entering the DDR data input mode after tDQSS, data is written from DQ[7:0] to the cache register on each and every rising and falling edge of DQS (center-aligned) when CLK is running and the DQS to CLK skew meets tDSH and tDSS, CE# is LOW, W/R# is HIGH, and ALE and CLE are HIGH on the rising edge of CLK. To exit DDR data input mode, the following conditions must be met: * CLK is running and the DQS to CLK skew meets tDSH and tDSS * CE# is LOW * W/R# is HIGH
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* ALE and CLE are latched LOW on the rising edge of CLK * The final two data bytes of the data input sequence are written to DQ[7:0] to the cache register on the rising and falling edges of DQS after the last cycle in the data input sequence in which ALE and CLE are latched HIGH. * DQS is held LOW for tWPST (after the final falling edge of DQS) Following tWPST, the bus enters bus idle mode and tCAD begins on the next rising edge of CLK. After tCAD starts, the host can disable the target if desired. Data input is ignored by die (LUNs) that are not selected or are busy. Figure 33: Synchronous DDR Data Input Cycles
tCS tCH
CE#
tCALS tCALS tCALH
CLE
tCALS tCAD
tCALS
tCALH
ALE
tCKL tCKH
tCALS
tCALH
tCALS
tCALH
CLK
tCK
tCAD starts here1
W/R#
tDQSS tDSH tDSS tDSH tDSH tDSS tDSH tDSS
DQS
tWPRE tDQSH tDQSL tDQSH tDQSL tDQSH tWPST
DQ[7:0]
tDS
D0
D1
tDH
D2
D3
DN-2
DN-1
tDS
DN
tDH
Don't Care
Notes:
1. When CE# remains LOW, tCAD begins at the first rising edge of the clock after tWPST completes. 2. tDSH (MIN) generally occurs during tDQSS (MIN). 3. tDSS (MIN) generally occurs during tDQSS (MAX).
Synchronous DDR Data Output
Data can be output from a die (LUN) if it is ready. Data output is supported following a READ operation from the NAND Flash array. To enter the DDR data output mode, the following conditions must be met: * * * * CLK is running CE# is LOW The host has released the DQ[7:0] bus and DQS W/R# is latched LOW on the rising edge of CLK to enable the selected die (LUN) to take ownership of the DQ[7:0] bus and DQS within tWRCK * tCAD is met * ALE and CLE are HIGH on the rising edge of CLK 43
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Upon entering the DDR data output mode, DQS will toggle HIGH and LOW with a delay of tDQSCK from the respective rising and falling edges of CLK. DQ[7:0] will output data edge-aligned to the rising and falling edges of DQS, with the first transition delayed by no more than tAC. DDR data output mode continues as long as CLK is running, CE# is LOW, W/R# is LOW, and ALE and CLE are HIGH on the rising edge of CLK. To exit DDR data output mode, the following conditions must be met: * * * * CLK is running CE# is LOW W/R# is LOW ALE and CLE are latched LOW on the rising edge of CLK
The final two data bytes are output on DQ[7:0] on the final rising and falling edges of DQS. The final rising and falling edges of DQS occur tDQSCK after the last cycle in the data output sequence in which ALE and CLE are latched HIGH. After tCKWR, the bus enters bus idle mode and tCAD begins on the next rising edge of CLK. Once tCAD starts the host can disable the target if desired. Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); however, it is possible to output data from the status register even when a die (LUN) is busy by issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command.
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Figure 34: Synchronous DDR Data Output Cycles
tCS tCH
CE#
tCALS tCALS tCALH
CLE
tCALS tCAD
tCALS
tCALH
ALE
tCKL tCKH
tCALS
tCALH
tCALS
tCALH
CLK
tCK tCALS tWRCK tDQSD
tHP
tHP
tHP tDQSCK tDQSCK
tHP
tHP
tHP tCKWR tDQSCK tDQSCK tCAD sta rts here1 tCALS tDQSHZ
W/R#
tDQSCK
tDQSCK
DQS
tAC tDVW
D0
tDVW
D1
tDVW
D2 DN-2
tDVW
DN-1
tDVW
DN
DQ[7:0]
tDQSQ
tDQSQ tQH tQH
tDQSQ
tQH
tDQSQ tQH
Undefined (d riven by NAN D)
Don't Care
Data Transitioning
Notes:
1. When CE# remains LOW, tCAD begins at the rising edge of the clock after tCKWR for subsequent command or data output cycle(s). 2. See Figure 31 (page 41) for details of W/R# behavior. 3. tAC is the DQ output window relative to CLK and is the long-term component of DQ skew. 4. For W/R# transitioning HIGH, DQ[7:0] and DQS go to tri-state. 5. For W/R# transitioning LOW, DQ[7:0] drives current state and DQS goes LOW. 6. After final data output, DQ[7:0] is driven until W/R# goes HIGH, but is not valid.
Write Protect
See Write Protect (page 33).
Ready/Busy#
See Ready/Busy# (page 33).
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Device Initialization
Some NAND Flash devices do not support VCCQ. For these devices all references to VCCQ are replaced with VCC. Micron NAND Flash devices are designed to prevent data corruption during power transitions. VCC is internally monitored. (The WP# signal supports additional hardware protection during power transitions.) When ramping VCC and VCCQ, use the following procedure to initialize the device: 1. Ramp VCC. 2. Ramp VCCQ. VCCQ must not exceed VCC. 3. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to any target (see Figure 35). The R/B# signal becomes valid when 50s has elapsed since the beginning the VCC ramp, and 10s has elapsed since VCCQ reaches VCCQ (MIN) and VCC reaches VCC (MIN). 4. If not monitoring R/B#, the host must wait at least 100s after VCCQ reaches VCCQ (MIN) and VCC reaches VCC (MIN). If monitoring R/B#, the host must wait until R/B# is HIGH. 5. The asynchronous interface is active by default for each target. Each LUN draws less than an average of 10mA (IST) measured over intervals of 1ms until the RESET (FFh) command is issued. 6. The RESET (FFh) command must be the first command issued to all targets (CE#s) after the NAND Flash device is powered on. Each target will be busy for tPOR after a RESET command is issued. The RESET busy time can be monitored by polling R/B# or issuing the READ STATUS (70h) command to poll the status register. 7. The device is now initialized and ready for normal operation. At power-down, VCCQ must go LOW, either before, or simultaneously with, VCC going LOW. Figure 35: R/B# Power-On Behavior
50s (MIN) Vccq = Vccq (MIN)
Vccq
Vcc = Vcc (MIN)
10s (MAX)
Vcc
> 0s
R/B#
Vcc ramp starts
100s (MAX) Invalid
Reset (FFh) is issued
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Note:
1. Disregard VCCQ for devices that use only VCC.
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Activating Interfaces
After performing the steps under Device Initialization (page 46), the asynchronous interface is active for all targets on the device. Each target's interface is independent of other targets, so the host is responsible for changing the interface for each target. If the host and NAND Flash device, through error, are no longer using the same interface, then steps under Activating the Asynchronous Interface are performed to resynchronize the interfaces.
Activating the Asynchronous Interface
To activate the asynchronous NAND interface, once the synchronous interface is active, the following steps are repeated for each target: 1. The host pulls CE# HIGH, disables its input to CLK, and enables its asynchronous interface. 2. The host pulls CE# LOW and issues the RESET (FFh) command, using an asynchronous command cycle. 3. R/B# goes LOW for tRST. 4. After tITC, and during tRST, the device enters the asynchronous NAND interface. READ STATUS (70h) and READ STATUS ENHANCED (78h) are the only commands that can be issued. 5. After tRST, R/B# goes HIGH. Timing mode feature address (01h), subfeature parameter P1 is set to 00h, indicating that the asynchronous NAND interface is active and that the device is set to timing mode 0. For further details, see Reset Operations.
Activating the Synchronous Interface
To activate the synchronous NAND Flash interface, the following steps are repeated for each target: 1. Issue the SET FEATURES (EFh) command. 2. Write address 01h, which selects the timing mode. 3. Write P1 with 1Xh, where "X" is the timing mode used in the synchronous interface (see Configuration Operations). 4. Write P2-P4 as 00h-00h-00h. 5. R/B# goes LOW for tITC. The host should pull CE# HIGH. During tITC, the host should not issue any type of command, including status commands, to the NAND Flash device. 6. After tITC, R/B# goes HIGH and the synchronous interface is enabled. Before pulling CE# LOW, the host should enable the clock.
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Figure 36: Activating the Synchronous Interface
CE# may transition HIGH CE# may transition LOW
A
B
C
Cycle type
CMD ADDR tADL
DIN
DIN
DIN
DIN
DQ[7:0]
EFh
01h
TM
P2
P3
P4 tWB tITC
R/B#
tCAD 100ns
Note:
1. TM = Timing mode.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Command Definitions
Command Definitions
Table 5: Command Set
Number of Valid Address Cycles 0 0 1 1 1 1 1 0 3 2 5 2 5 0 5 5 0 5 0 5 5 5 Data Input Cycles - - - - - - 4 - - - - Optional Optional - - - - - - Yes Yes Yes Valid While Command Selected LUN Cycle #2 is Busy1 - - - - - - - - - E0h E0h - - - 30h 32h - 31h - 10h 11h 15h Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 8 7 6,7 7 6 5 3 4 Yes Yes Valid While Other LUNs are Busy2 Yes Yes 3
Command Reset Operations RESET SYNCHRONOUS RESET
Command Cycle #1 FFh FCh 90h ECh EDh EEh EFh 70h 78h 05h 06h 85h 85h 00h 00h 00h 31h 00h 3Fh 80h 80h 80h
Notes
Identification Operations READ ID READ PARAMETER PAGE READ UNIQUE ID Configuration Operations GET FEATURES SET FEATURES Status Operations READ STATUS READ STATUS ENHANCED CHANGE READ COLUMN CHANGE READ COLUMN ENHANCED CHANGE WRITE COLUMN CHANGE ROW ADDRESS Read Operations READ MODE READ PAGE READ PAGE MULTIPLANE READ PAGE CACHE SEQUENTIAL READ PAGE CACHE RANDOM READ PAGE CACHE LAST Program Operations PROGRAM PAGE www..com PROGRAM PAGE MULTI-PLANE PROGRAM PAGE CACHE Erase Operations
Column Address Operations
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Table 5: Command Set (Continued)
Number of Valid Address Cycles 3 3 Data Input Cycles - - Valid While Command Selected LUN Cycle #2 is Busy1 D0h D1h Valid While Other LUNs are Busy2 Yes Yes
Command ERASE BLOCK ERASE BLOCK MULTI-PLANE Copyback Operations COPYBACK READ COPYBACK PROGRAM COPYBACK PROGRAM MULTI-PLANE
Command Cycle #1 60h 60h
Notes
00h 85h 85h
5 5 5
- Optional Optional
35h 10h 11h
Yes Yes Yes
6
Notes:
1. Busy means RDY = 0. 2. These commands can be used for interleaved die (multi-LUN) operations (see Interleaved Die (Multi-LUN) Operations (page 106)). 3. The READ ID (90h) and GET FEATURES (EEh) output identical data on rising and falling DQS edges. 4. The SET FEATURES (EFh) command requires data transition prior to the rising edge of CLK, with identical data for the rising and falling edges. 5. Command cycle #2 of 11h is conditional. See CHANGE ROW ADDRESS (85h) (page 77) for more details. 6. This command can be preceded by up to one READ PAGE MULTI-PLANE (00h-32h) command to accommodate a maximum simultaneous two-plane array operation. 7. Issuing a READ PAGE CACHE-series (31h, 00h-31h, 00h-32h, 3Fh) command when the array is busy (RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h) or READ PAGE CACHE-series command; otherwise, it is prohibited. 8. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1, ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE (80h-15h) command; otherwise, it is prohibited.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Reset Operations
Reset Operations
RESET (FFh)
The RESET (FFh) command is used to put a target into a known condition and to abort command sequences in progress. This command is accepted by all die (LUNs), even when they are busy. When FFh is written to the command register, the target goes busy for tRST. During tRST, the selected target (CE#) discontinues all array operations on all die (LUNs). All pending single- and multi-plane operations are cancelled. If this command is issued while a PROGRAM or ERASE operation is occurring on one or more die (LUNs), the data may be partially programmed or erased and is invalid. The command register is cleared and ready for the next command. The data register and cache register contents are invalid. RESET must be issued as the first command to each target following power-up (see Device Initialization (page 46)). Use of the READ STATUS ENHANCED (78h) command is prohibited during the power-on RESET. To determine when the target is ready, use READ STATUS (70h). If the RESET (FFh) command is issued when the synchronous interface is enabled, the target's interface is changed to the asynchronous interface and the timing mode is set to 0. The RESET (FFh) command can be issued asynchronously when the synchronous interface is active, meaning that CLK does not need to be continuously running when CE# is transitioned LOW and FFh is latched on the rising edge of CLK. After this command is latched, the host should not issue any commands during tITC. After tITC, and during or after tRST, the host can poll each LUN's status register. If the RESET (FFh) command is issued when the asynchronous interface is active, the target's asynchronous timing mode remains unchanged. During or after tRST, the host can poll each LUN's status register. Figure 37: RESET (FFh) Operation
Cycle type
Command
DQ[7:0]
FFh
tWB tRST
R/B#
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Reset Operations SYNCHRONOUS RESET (FCh)
When the synchronous interface is active, the SYNCHRONOUS RESET (FCh) command is used to put a target into a known condition and to abort command sequences in progress. This command is accepted by all die (LUNs), even when they are BUSY. When FCh is written to the command register, the target goes busy for tRST. During tRST, the selected target (CE#) discontinues all array operations on all die (LUNs). All pending single- and multi-plane operations are cancelled. If this command is issued while a PROGRAM or ERASE operation is occurring on one or more die (LUNs), the data may be partially programmed or erased and is invalid. The command register is cleared and ready for the next command. The data register and cache register contents are invalid and the synchronous interface remains active. During or after tRST, the host can poll each LUN's status register. SYNCHRONOUS RESET is only accepted while the synchronous interface is active. Its use is prohibited when the asynchronous interface is active. Figure 38: SYNCHRONOUS RESET (FCh) Operation
Cycle type
Command
DQ[7:0]
FCh
tWB tRST
R/B#
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Identification Operations
Identification Operations
READ ID (90h)
The READ ID (90h) command is used to read identifier codes programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing 90h to the command register puts the target in read ID mode. The target stays in this mode until another valid command is issued. When the 90h command is followed by a 00h address cycle, the target returns a 5-byte identifier code that includes the manufacturer ID, device configuration, and part-specific information. When the 90h command is followed by a 20h address cycle, the target returns the 4-byte ONFI identifier code. After the 90h and address cycle are written to the target, the host enables data output mode to read the identifier information. When the asynchronous interface is active, one data byte is output per RE# toggle. When the synchronous interface is active, one data byte is output per rising edge of DQS when ALE and CLE are HIGH; the data byte on the falling edge of DQS is identical to the data byte output on the previous rising edge of DQS. Figure 39: READ ID (90h) with 00h Address Operation
Cycle type
Command Address tWHR Dout Dout Dout Dout Dout Dout Dout Dout
DQ[7:0]
90h
00h
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Note:
1. See the READ ID Parameter tables for byte definitions.
Figure 40: READ ID (90h) with 20h Address Operation
Cycle type
Command Address tWHR Dout Dout Dout Dout
DQ[7:0]
90h
20h
4Fh
4Eh
46h
49h
Note:
1. See the READ ID Parameter tables for byte definitions.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND READ ID Parameter Tables
READ ID Parameter Tables
Table 6: Read ID Parameters for Address 00h
Device MT29F16G08ABABA MT29F16G08ABCBB MT29F32G08AFABA MT29F32G08AECBB MT29F64G08AJABA MT29F64G08AKABA MT29F64G08AKCBB MT29F64G08AMABA MT29F64G08AMCBB MT29F128G08AUABA MT29F128G08AUCBB Note: Byte 0 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch Byte 1 48h 48h 48h 48h 68h 68h 68h 48h 48h 68h 68h Byte 2 00h 00h 00h 00h 01h 01h 01h 00h 00h 01h 01h Byte 3 26h 26h 26h 26h A6h A6h A6h 26h 26h A6h A6h Byte 4 89h 89h 89h 89h 89h 89h 89h 89h 89h 89h 89h Byte 5 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Byte 6 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Byte 7 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
1. h = hexadecimal.
Table 7: Read ID Parameters for Address 20h
Device All Notes: Byte 0 4Fh 1. h = hexadecimal. 2. XXh = Undefined. Byte 1 4Eh Byte 2 46h Byte 3 49h Byte 4 XXh
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Configuration Operations
Configuration Operations
The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the target's default power-on behavior. These commands use a one-byte feature address to determine which subfeature parameters will be read or modified. Each feature address (in the 00h to FFh range) is defined in Table 8. The SET FEATURES (EFh) command writes subfeature parameters (P1-P4) to the specified feature address. The GET FEATURES command reads the subfeature parameters (P1-P4) at the specified feature address. Unless otherwise specifed, the values of the feature addresses do not change when RESET (FFh, FCh) is issued by the host. Table 8: Feature Address Definitions
Feature Address 00h 01h 02h-0Fh 10h 11h-7Fh 80h 81h 82h-8Fh 90h 91h-FFh Definition Reserved Timing mode Reserved Programmable output drive strength Reserved Programmable output drive strength Programmable RB# pull-down strength Reserved Array operation mode Reserved
SET FEATURES (EFh)
The SET FEATURES (EFh) command writes the subfeature parameters (P1-P4) to the specified feature address to enable or disable target-specific features. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EFh to the command register puts the target in the set features mode. The target stays in this mode until another command is issued. The EFh command is followed by a valid feature address as specified in Table 8. The host waits for tADL before the subfeature parameters are input. When the asynchronous interface is active, one subfeature parameter is latched per rising edge of WE#. When the synchronous interface is active, one subfeature parameter is latched per rising edge of DQS. The data on the falling edge of DQS should be identical to the subfeature parameter input on the previous rising edge of DQS. The device is not required to wait for the repeated data byte before beginning internal actions.
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After all four subfeature parameters are input, the target goes busy for tFEAT. The READ STATUS (70h) command can be used to monitor for command completion. Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to modify the interface type, the target will be busy for tITC. See Activating Interfaces (page 47) for details.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Configuration Operations
Figure 41: SET FEATURES (EFh) Operation
Cycle type
Command Address tADL Din Din Din Din
DQ[7:0]
EFh
FA
P1
P2
P3
P4 tWB tFEAT
R/B#
GET FEATURES (EEh)
The GET FEATURES (EEh) command reads the subfeature parameters (P1-P4) from the specified feature address. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EEh to the command register puts the target in get features mode. The target stays in this mode until another valid command is issued. When the EEh command is followed by a feature address, the target goes busy for tFEAT. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. During and prior to data output, use of the READ STATUS ENHANCED (78h) command is prohibited. After tFEAT completes, the host enables data output mode to read the subfeature parameters. When the asynchronous interface is active, one data byte is output per RE# toggle. When the synchronous interface is active, one subfeature parameter is output per DQS toggle on rising or falling edge of DQS. Figure 42: GET FEATURES (EEh) Operation
Cycle type
Command Address DOUT DOUT DOUT DOUT
DQ[7:0]
EEh
FA tWB tFEAT tRR
P1
P2
P3
P4
R/B#
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Configuration Operations
Table 9: Feature Address 01h: Timing Mode
Subfeature Parameter Options P1 Timing mode Mode 0 (default) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Data interface Asynchronous (default) Synchronous DDR Reserved Reserved P2 Reserved P3 Reserved P4 Reserved Notes: 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 1 0 1 x 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 x0h x1h x2h x3h x4h x5h 0xh 1xh 2xh 00b 1 1, 2 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
1. Asynchronous timing mode 0 is the default, power-on value. 2. If the synchronous interface is active, a RESET (FFh) command will change the timing mode and data interface bits of feature address 01h to their default values. If the asynchronous interface is active, a RESET (FFh) command will not change the values of the timing mode or data interface bits to their default valued.
Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength
Subfeature Parameter P1 Output drive strength Overdrive 2 Overdrive 1 Nominal (default) Underdrive Reserved www..com P2 Reserved P3 Reserved 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 00h 01h 02h 03h 00h 00h 1 Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
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Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength (Continued)
Subfeature Parameter P4 Reserved Note: 0 0 0 0 0 0 0 0 00h Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
1. See Output Drive Impedance (page 108) for details.
Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength
Subfeature Parameter P1 R/B# pull-down strength Full (default) Three-quarter One-half One-quarter Reserved P2 Reserved P3 Reserved P4 Reserved Note: 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 1 1 0 1 0 1 00h 01h 02h 03h 00h 1 Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
1. This feature address is used to change the default R/B# pull-down strength. Its strength should be selected based on the expected loading of R/B#. Full strength is the default, power-on value.
Table 12: Feature Addresses 90h: Array Operation Mode
Subfeature Parameter P1 Array Operation Mode Reserved P2 Reserved www..com P3 Reserved P4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00h 00h Normal (default) OTP Block 0 0 0 0 0 0 0 0 1 00h 01h 00h 1 Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
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Table 12: Feature Addresses 90h: Array Operation Mode (Continued)
Subfeature Parameter Reserved Notes: Options DQ7 0 DQ6 0 DQ5 0 DQ4 0 DQ3 0 DQ2 0 DQ1 0 DQ0 0 Value 00h Notes
1. See One-Time Programmable (OTP) Operations for details. 2. A RESET (FFh) command will cause the bits of the array operation mode to change to their default values.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND READ PARAMETER PAGE (ECh)
READ PARAMETER PAGE (ECh)
The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing ECh to the command register puts the target in read parameter page mode. The target stays in this mode until another valid command is issued. When the ECh command is followed by an 00h address cycle, the target goes busy for tR. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. Use of the READ STATUS ENHANCED (78h) command is prohibited while the target is busy and during data output. After tR completes, the host enables data output mode to read the parameter page. When the asynchronous interface is active, one data byte is output per RE# toggle. When the synchronous interface is active, one data byte is output for each rising or falling edge of DQS. A minimum of three copies of the parameter page are stored in the device. Each parameter page is 256 bytes. If desired, the CHANGE READ COLUMN (05h-E0h) command can be used to change the location of data output. Use of the CHANGE READ COLUMN ENHANCED (06h-E0h) command is prohibited. The READ PARAMETER PAGE (ECh) output data can be used by the host to configure its internal settings to properly use the NAND Flash device. Parameter page data is static per part, however the value can be changed through the product cycle of NAND Flash. The host should interpret the data and configure itself accordingly. Figure 43: READ PARAMETER (ECh) Operation
Cycle type
Command Address Dout Dout Dout Dout Dout Dout
DQ[7:0]
ECh
00h tWB tR tRR
P00
P10
...
P01
P11
...
R/B#
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure
Byte 0-3 Description Parameter page signature Byte 0: 4Fh, "O" Byte 1: 4Eh, "N" Byte 2: 46h, "F" Byte 3: 49h, "I" Revision number Bit[15:4]: Reserved (0) Bit 3: 1 = supports ONFI verion 2.1 Bit 2: 1 = supports ONFI version 2.0 Bit 1: 1 = supports ONFI version 1.0 Bit 0: Reserved (0) Features supported Bit[15:8]: Reserved (0) Bit 7: 1 = supports extended parameter page Bit 6: 1 = supports interleaved (multi-plane) read operations Bit 5: 1 = supports synchronous interface Bit 4: 1 = supports odd-to-even page copyback Bit 3: 1 = supports interleaved (multi-plane) program and erase operations Bit 2: 1 = supports non-sequential page programming Bit 1: 1 = supports multiple LUN operations Bit 0: 1 = supports 16-bit data bus width Optional commands supported Bit[15:9]: Reserved (0) Bit 8: 1 = supports small data move Bit 7: 1 = supports CHANGE ROW ADDRESS Bit 6: 1 = supports CHANGE READ COLUMN ENHANCED Bit 5: 1 = supports READ UNIQUE ID Bit 4: 1 = supports COPYBACK Bit 3: 1 = supports READ STATUS ENHANCED Bit 2: 1 = supports GET FEATURES and SET FEATURES Bit 1: 1 = supports read cache commands Bit 0: 1 = supports PROGRAM PAGE CACHE Reserved (0) Device - Values 4Fh, 4Eh, 46h, 49h
Revision information and features block
4-5
-
0Eh, 00h
6-7
MT29F16G08ABABA MT29F32G08AFABA MT29F64G08AMABA MT29F64G08AJABA MT29F64G08AKABA MT29F128G08AUABA MT29F16G08ABCBB MT29F32G08AECBB MT29F64G08AMCBB MT29F64G08AKCBB MT29F128G08AUCBB -
58h, 00h
5Ah, 00h
78h, 00h
7Ah, 00h FFh, 01h
8-9
10-11
- - - -
All 00h All 00h 03h All 00h
12-13 Reserved (0) www..com 14 Number of parameter pages 15-31 Reserved (0) Manufacturer information block
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure (Continued)
Byte 32-43 Description Device manufacturer (12 ASCII characters) Micron Device model (20 ASCII characters) Device - Values 4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 31h, 36h, 47h, 30h, 38h, 41h, 42h, 41h, 42h, 41h, 57h, 50h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 33h, 32h, 47h, 30h, 38h, 41h, 46h, 41h, 42h, 41h, 57h, 50h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 41h, 4Ah, 41h, 42h, 41h, 57h, 50h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 41h, 4Bh, 41h, 42h, 41h, 43h, 35h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 41h, 4Dh, 41h, 42h, 41h, 43h, 35h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 41h, 55h, 41h, 42h, 41h, 43h, 35h, 20h, 20h
44-63
MT29F16G08ABABAWP
MT29F32G08AFABAWP
MT29F64G08AJABAWP
MT29F64G08AKABAC5
MT29F64G08AMABAC5
MT29F128G08AUABAC5
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure (Continued)
Byte Description Device MT29F16G08ABCBBH1 Values 4Dh, 54h, 32h, 39h, 46h, 31h, 36h, 47h, 30h, 38h, 41h, 42h, 43h, 42h, 42h, 48h, 31h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 33h, 32h, 47h, 30h, 38h, 41h, 45h, 43h, 42h, 42h, 48h, 31h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 41h, 4Bh, 43h, 42h, 42h, 48h, 32h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 41h, 4Dh, 43h, 42h, 42h, 48h, 32h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 41h, 55h, 43h, 42h, 42h, 48h, 33h, 20h, 20h 2Ch 00h, 00h All 00h 00h, 10h, 00h, 00h E0h, 00h 00h, 02h, 00h, 00h 1Ch, 00h 80h, 00h, 00h, 00h 00h, 10h, 00h, 00h
MT29F32G08AECBBH1
MT29F64G08AKCBBH2
MT29F64G08AMCBBH2
MT29F128G08AUCBBH3
64 65-66 67-79 80-83 84-85 86-89 90-91 92-95 96-99
JEDEC manufacturer ID Date code Reserved (0) Number of data bytes per page Number of spare bytes per page Number of data bytes per partial page Number of spare bytes per partial page Number of pages per block Number of blocks per LUN
- - - - - - - - -
Memory organization block
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure (Continued)
Byte 100 Description Number of LUNs per chip enable Device MT29F16G08ABABA MT29F16G08ABCBB MT29F32G08AFABA MT29F32G08AECBB MT29F64G08AMABA MT29F64G08AMCBB MT29F64G08AJABA MT29F64G08AKABA MT29F64G08AKCBB MT29F128G08AUABA MT29F128G08AUCBB 101 Number of address cycles Bit[7:4]: Column address cycles Bit[3:0]: Row address cycles Number of bits per cell Bad blocks maximum per LUN Block endurance Guaranteed valid blocks at beginning of target Block endurance for guaranteed valid blocks Number of programs per page Partial programming attributes Bit[7:5]: Reserved Bit 4: 1 = partial page layout is partial page data followed by partial page spare Bit[3:1]: Reserved Bit 0: 1 = partial page programming has constraints Number of bits ECC correctability Number of interleaved address bits Bit[7:4]: Reserved (0) Bit[3:0]: Number of interleaved address bits - 23h 02h Values 01h
102 103-104 105-106 107 108-109 110 111
- - - - - - -
01h 50h, 00h 01h, 05h 01h 00h, 00h 04h 00h
112 113
- -
04h 01h
Interleaved operation attributes Bit[7:5]: Reserved (0) Bit 4: 1 = supports read cache Bit 3: Address restrictions for cache operations Bit 2: 1 = supports program cache Bit 1: 1 = no block address restrictions Bit 0: Overlapped/concurrent interleaving support www..com 115-127 Reserved (0) Electrical parameters block
114
-
1Eh
-
All 00h
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure (Continued)
Byte 128 Description I/O pin capacitance per chip enable Device MT29F16G08ABABAWP MT29F32G08AFABAWP MT29F64G08AJABAWP MT29F64G08AKABAC5 MT29F64G08AMABAC5 MT29F128G08AUABAC5 MT29F16G08ABCBBH1 MT29F32G08AECBBH1 MT29F64G08AKCBBH2 MT29F64G08AMCBBH2 MT29F128G08AUCBBH3 129-130 Timing mode support Bit[15:6]: Reserved (0) Bit 5: 1 = supports timing mode 5 Bit 4: 1 = supports timing mode 4 Bit 3: 1 = supports timing mode 3 Bit 2: 1 = supports timing mode 2 Bit 1: 1 = supports timing mode 1 Bit 0: 1 = supports timing mode 0, shall be 1 Program cache timing mode support Bit[15:6]: Reserved (0) Bit 5: 1 = supports timing mode 5 Bit 4: 1 = supports timing mode 4 Bit 3: 1 = supports timing mode 3 Bit 2: 1 = supports timing mode 2 Bit 1: 1 = supports timing mode 1 Bit 0: 1 = supports timing mode 0
tPROG tBERS tR
Values 05h 05h 09h 0Eh 07h 0Ah 05h 05h 09h 05h 09h 1Fh, 00h
-
131-132
-
1Fh, 00h
133-134 135-136 137-138 139-140
Maximum PROGRAM PAGE time (s)
- - - -
F4h, 01h ACh, 0Dh 19h, 00h C8h, 00h
Maximum BLOCK ERASE time (s)
Maximum PAGE READ time (s) Minimum change column setup time (ns)
tCCS
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure (Continued)
Byte 141-142 Description Source synchronous timing mode support Bit[15:6]: Reserved (0) Bit 5: 1 = supports timing mode 5 Bit 4: 1 = supports timing mode 4 Bit 3: 1 = supports timing mode 3 Bit 2: 1 = supports timing mode 2 Bit 1: 1 = supports timing mode 1 Bit 0: 1 = supports timing mode 0 Device MT29F16G08ABABAWP MT29F32G08AFABAWP MT29F64G08AJABAWP MT29F64G08AKABAC5 MT29F64G08AMABAC5 MT29F128G08AUABAC5 MT29F16G08ABCBBH1 MT29F32G08AECBBH1 MT29F64G08AKCBBH2 MT29F64G08AMCBBH2 MT29F128G08AUCBBH3 143 Source synchronous features Bit[7:3]: Reserved (0) Bit 2: 1 = devices support CLK stopped for data input Bit 1: 1 = typical capacitance values present Bit 0: 0 = use tCAD MIN value MT29F16G08ABABAWP MT29F32G08AFABAWP MT29F64G08AJABAWP MT29F64G08AKABAC5 MT29F64G08AMABAC5 MT29F128G08AUABAC5 MT29F16G08ABCBBH1 MT29F32G08AECBBH1 MT29F64G08AKCBBH2 MT29F64G08AMCBBH2 MT29F128G08AUCBBH3 144-145 CLK input pin capacitance, typical MT29F16G08ABABAWP MT29F32G08AFABAWP MT29F64G08AJABAWP MT29F64G08AKABAC5 MT29F64G08AMABAC5 MT29F128G08AUABAC5 MT29F16G08ABCBBH1 MT29F32G08AECBBH1 MT29F64G08AKCBBH2 MT29F64G08AMCBBH2 MT29F128G08AUCBBH3 3Eh, 00h 1Fh, 00h 35h, 00h 24h, 00h 00h, 00h 02h 00h 1Fh, 00h Values 00h, 00h
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure (Continued)
Byte 146-147 Description I/O pin capacitance, typical Device MT29F16G08ABABAWP MT29F32G08AFABAWP MT29F64G08AJABAWP MT29F64G08AKABAC5 MT29F64G08AMABAC5 MT29F128G08AUABAC5 MT29F16G08ABCBBH1 MT29F32G08AECBBH1 MT29F64G08AKCBBH2 MT29F64G08AMCBBH2 MT29F128G08AUCBBH3 148-149 Input capacitance, typical MT29F16G08ABABAWP MT29F32G08AFABAWP MT29F64G08AJABAWP MT29F64G08AKABAC5 MT29F64G08AMABAC5 MT29F128G08AUABAC5 MT29F16G08ABCBBH1 MT29F32G08AECBBH1 MT29F64G08AKCBBH2 MT29F64G08AMCBBH2 MT29F128G08AUCBBH3 150 Input pin capacitance, maximum MT29F16G08ABABAWP MT29F32G08AFABAWP MT29F64G08AJABAWP MT29F64G08AKABAC5 MT29F64G08AMABAC5 MT29F128G08AUABAC5 MT29F16G08ABCBBH1 MT29F32G08AECBBH1 MT29F64G08AKCBBH2 MT29F64G08AMCBBH2 MT29F128G08AUCBBH3 151 Driver strength support www..com Bit[7:3]: Reserved (0) Bit 2: 1 = Supports overdrive (2 drive strength) Bit 1: 1 = Supports overdrive (1 drive strength) Bit 0: 1 = Supports driver strength settings 152-153
tR
Values 00h, 00h
2Dh, 00h 50h, 00h 28h, 00h 49h, 00h 00h, 00h
28h, 00h 44h, 00h 22h, 00h 35h, 00h 0Ah 07h 09h 0Ah 05h 0Ah 05h 08h 04h 07h 07h
-
maximum interleaved (multi-plane) page read time (s)
-
19h, 00h
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure (Continued)
Byte 154-163 164-165 166 Description Reserved (0) Vendor-specific revision number TWO-PLANE PAGE READ support Bit[7:1]: Reserved (0) Bit 0: 1 = Support for TWO-PLANE PAGE READ Read cache support Bit[7:1]: Reserved (0) Bit 0: 0 = Does not support Micron-specific read cache function READ UNIQUE ID support Bit[7:1]: Reserved (0) Bit 0: 0 = Does not support Micron-specific READ UNIQUE ID Programmable DQ output impedance support Bit[7:1]: Reserved (0) Bit 0: 0 = No support for programmable DQ output impedance by B8h command Number of programmable DQ output impedance settings Bit[7:3]: Reserved (0) Bit [2:0] = Number of programmable DQ output impedance settings Programmable DQ output impedance feature address Bit[7:0] = Programmable DQ output impedance feature address Programmable R/B# pull-down strength support Bit[7:1]: Reserved (0) Bit 0: 1 = Support programmable R/B# pull-down strength Programmable R/B# pull-down strength feature address Bit[7:0] = Feature address used with programmable R/B# pull-down strength Number of programmable R/B# pull-down strength settings Bit[7:3]: Reserved (0) Bit[2:0] = Number of programmable R/B# pull-down strength settings Device - - - Values All 00h 01h, 00h 01h
Vendor block
167
-
00h
168
-
00h
169
-
00h
170
-
04h
171
-
10h
172
-
01h
173
-
81h
174
-
04h
OTP mode support Bit[7:2]: Reserved (0) Bit 1: 1 = Supports Get/Set Features command set www..com Does not support A5h/A0h/AFh OTP command Bit 0: 0 = set 176 OTP page start Bit[7:0] = Page where OTP page space begins
175
-
02h
-
02h
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Parameter Page Data Structure Tables
Table 13: Parameter Page Data Structure (Continued)
Byte 177 Description OTP DATA PROTECT address Bit[7:0] = Page address to use when issuing OTP DATA PROTECT command Number of OTP pages Bit[15:5]: Reserved (0) Bit[4:0] = Number of OTP pages OTP Feature Address Reserved (0) Parameter page revision Integrity CRC Device - Values 01h
178
-
1Eh
179 180-252 253 254-255
- - - MT29F16G08ABABAWP MT29F32G08AFABAWP MT29F64G08AJABAWP MT29F64G08AKABAC5 MT29F64G08AMABAC5 MT29F128G08AUABAC5 MT29F16G08ABCBBH1 MT29F32G08AECBBH1 MT29F64G08AKCBBH2 MT29F64G08AMCBBH2 MT29F128G08AUCBBH3
90h All 00h 03h B4h, ADh BBh, A8h F7h, D2h 20h, 7Dh 2Ch, 10h AEh, E7h D9h, AAh 53h, 74h 3Fh, CCh 30h, 75h EBh, C5h See bytes 0-255 See bytes 0-255 All FFh
Redundant parameter pages 256-511 512-767 Value of bytes 0-255 Value of bytes 0-255 - - -
768-4319 Reserved (FFh)
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND READ UNIQUE ID (EDh)
READ UNIQUE ID (EDh)
The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EDh to the command register puts the target in read unique ID mode. The target stays in this mode until another valid command is issued. When the EDh command is followed by a 00h address cycle, the target goes busy for tR. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. After tR completes, the host enables data output mode to read the unique ID. When the asynchronous interface is active, one data byte is output per RE# toggle. When the synchronous interface is active, two data bytes are output, one byte for each rising or falling edge of DQS. Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the complement of the first 16 bytes. The host should XOR the first 16 bytes with the second 16 bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In the event that a non-FFh result is returned, the host can repeat the XOR operation on a subsequent copy of the unique ID data. If desired, the CHANGE READ COLUMN (05hE0h) command can be used to change the data output location. Use of the CHANGE READ COLUMN ENHANCED (06h-E0h) command is prohibited. Figure 44: READ UNIQUE ID (EDh) Operation
Cycle type
Command Address Dout Dout Dout Dout Dout Dout
DQ[7:0]
EDh
00h tWB tR tRR
U00
U10
...
U01
U11
...
R/B#
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Status Operations
Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same target through its 8-bit status register. After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued, status register output is enabled. The contents of the status register are returned on DQ[7:0] for each data output request. When the asynchronous interface is active and status register output is enabled, changes in the status register are seen on DQ[7:0] as long as CE# and RE# are LOW; it is not necessary to toggle RE# to see the status register update. When the synchronous interface is active and status register output is enabled, changes in the status register are seen on DQ[7:0] as long as CE# and W/R# are LOW and ALE and CLE are HIGH. DQS also toggles while ALE and CLE are HIGH. While monitoring the status register to determine when a data transfer from the Flash array to the data register (tR) is complete, the host must issue the READ MODE (00h) command to disable the status register and enable data output (see READ MODE (00h) (page 81)). The READ STATUS (70h) command returns the status of the most recently selected die (LUN). To prevent data contention during or following an interleaved die (multi-LUN) operation, the host must enable only one die (LUN) for status output by using the READ STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations (page 106)). Table 14: Status Register Definition
SR Bit 7 Definition WP# Independent per Plane1 - Description Write Protect: 0 = Protected 1 = Not protected In the normal array mode, this bit indicates the value of the WP# signal. In OTP mode this bit is set to 0 if a PROGRAM OTP PAGE operation is attempted and the OTP area is protected. Ready/Busy I/O: 0 = Busy 1 = Ready This bit indicates that the selected die (LUN) is not available to accept new commands, address, or data I/O cycles with the exception of RESET (FFh), SYNCHRONOUS RESET (FCh), READ STATUS (70h), and READ STATUS ENHANCED (78h). This bit applies only to the selected die (LUN). Ready/Busy Array: 0 = Busy 1 = Ready This bit goes LOW (busy) when an array operation is occurring on any plane of the selected die (LUN). It goes HIGH when all array operations on the selected die (LUN) finish. This bit applies only to the selected die (LUN). Reserved (0) Reserved (0)
6
RDY
-
5
ARDY
-
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- -
- -
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Status Operations
Table 14: Status Register Definition (Continued)
SR Bit 2 1 Definition - FAILC Independent per Plane1 - Yes Reserved (0) Pass/Fail (N-1): 0 = Pass 1 = Fail This bit is set if the previous operation on the selected die (LUN) failed. This bit is valid only when RDY (SR bit 6) is 1. It applies to PROGRAM-, and COPYBACK PROGRAM-series operations (80h-10h, 80h-15h, 85h-10h). This bit is not valid following an ERASE-sereis or READ-series operation. Pass/Fail (N): 0 = Pass 1 = Fail This bit is set if the most recently finished operation on the selected die (LUN) failed. This bit is valid only when ARDY (SR bit 5) is 1. It applies to PROGRAM-, ERASE-, and COPYBACK PROGRAM-series operations (80h-10h, 80h-15h, 60h-D0h, 85h-10h). This bit is not valid following a READ-series operation. Description
0
FAIL
Yes
Note:
1. After a multi-plane operation begins, the FAILC and FAIL bits are ORed together for the active planes when the READ STATUS (70h) command is issued. After the READ STATUS ENHANCED (78h) command is issued, the FAILC and FAIL bits reflect the status of the plane selected.
READ STATUS (70h)
The READ STATUS (70h) command returns the status of the last-selected die (LUN) on a target. This command is accepted by the last-selected die (LUN) even when it is busy (RDY = 0). If there is only one die (LUN) per target, the READ STATUS (70h) command can be used to return status following any NAND command. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select the die (LUN) that should report status. In this situation, using the READ STATUS (70h) command will result in bus contention, as two or more die (LUNs) could respond until the next operation is issued. The READ STATUS (70h) command can be used following all single die (LUN) operations. If following a multi-plane operation, regardless of the number of LUNs per target, the READ STATUS (70h) command indicates an error occurred (FAIL = 1), use the READ STATUS ENHANCED (78h) command--once for each plane--to determine which plane operation failed.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Status Operations
Figure 45: READ STATUS (70h) Operation
Cycle type
Command tWHR
Dout
DQ[7:0]
70h
SR
READ STATUS ENHANCED (78h)
The READ STATUS ENHANCED (78h) command returns the status of the addressed die (LUN) on a target even when it is busy (RDY = 0). This command is accepted by all die (LUNs), even when they are BUSY (RDY = 0). Writing 78h to the command register, followed by three row address cycles containing the page, block, and LUN addresses, puts the selected die (LUN) into read status mode.The selected die (LUN) stays in this mode until another valid command is issued. Die (LUNs) that are not addressed are deselected to avoid bus contention. The selected LUN's status is returned when the host requests data output. The RDY and ARDY bits of the status register are shared for all of the planes of the selected die (LUN). The FAILC and FAIL bits are specific to the plane specified in the row address. The READ STATUS ENHANCED (78h) command also enables the selected die (LUN) for data output. To begin data output following a READ-series operation after the selected die (LUN) is ready (RDY = 1), issue the READ MODE (00h) command, then begin data output. If the host needs to change the cache register that will output data, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command after the die (LUN) is ready (see CHANGE READ COLUMN ENHANCED (06h-E0h) (page 75)). Use of the READ STATUS ENHANCED (78h) command is prohibited during the poweron RESET (FFh) command and when OTP mode is enabled. It is also prohibited following some of the other reset, identification, and configuration operations. See individual operations for specific details. Figure 46: READ STATUS ENHANCED (78h) Operation
Cycle type
Command Address Address Address tWHR Dout
DQx
78h
R1
R2
R3
SR
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Column Address Operations
Column Address Operations
The column address operations affect how data is input to and output from the cache registers within the selected die (LUNs). These features provide host flexibility for managing data, especially when the host internal buffer is smaller than the number of data bytes or words in the cache register. When the asynchronous interface is active, column address operations can address any byte in the selected cache register. When the synchronous interface is active, column address operations are aligned to word boundaries (CA0 is forced to 0), because as data is transferred on DQ[7:0] in twobyte units.
CHANGE READ COLUMN (05h-E0h)
The CHANGE READ COLUMN (05h-E0h) command changes the column address of the selected cache register and enables data output from the last selected die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during CACHE READ operations (RDY = 1; ARDY = 0). Writing 05h to the command register, followed by two column address cycles containing the column address, followed by the E0h command, puts the selected die (LUN) into data output mode. After the E0h command cycle is issued, the host must wait at least tCCS before requesting data output. The selected die (LUN) stays in data output mode until another valid command is issued. In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be issued prior to issuing the CHANGE READ COLUMN (05h-E0h). In this situation, using the CHANGE READ COLUMN (05h-E0h) command without the READ STATUS ENHANCED (78h) command will result in bus contention, as two or more die (LUNs) could output data. Figure 47: CHANGE READ COLUMN (05h-E0h) Operation
Cycle type
DOUT
DOUT
Command
tRHW
Address
Address
Command
tCCS
DOUT
DOUT
DOUT
DQ[7:0]
Dn
Dn + 1
05h
C1
C2
E0h
Dk
Dk + 1
Dk + 2
SR[6]
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Column Address Operations CHANGE READ COLUMN ENHANCED (06h-E0h)
The CHANGE READ COLUMN ENHANCED (06h-E0h) command enables data output on the addressed die's (LUN's) cache register at the specified column address. This command is accepted by a die (LUN) when it is ready (RDY = 1; ARDY = 1). Writing 06h to the command register, followed by two column address cycles and three row address cycles, followed by E0h, enables data output mode on the address LUN's cache register at the specified column address. After the E0h command cycle is issued, the host must wait at least tCCS before requesting data output. The selected die (LUN) stays in data output mode until another valid command is issued. Following a multi-plane read page operation, the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select the cache register to be enabled for data output. After data output is complete on the selected plane, the command can be issued again to begin data output on another plane. In devices with more than one die (LUN) per target, after all of the die (LUNs) on the target are ready (RDY = 1), the CHANGE READ COLUMN ENHANCED (06h-E0h) command can be used following an interleaved die (multi-LUN) read operation. Die (LUNs) that are not addressed are deselected to avoid bus contention. In devices with more than one die (LUN) per target, during interleaved die (multi-LUN) operations where more than one or more die (LUNs) are busy (RDY = 1; ARDY = 0 or RDY = 0; ARDY = 0), the READ STATUS ENHANCED (78h) command must be issued to the die (LUN) to be selected prior to issuing the CHANGE READ COLUMN ENHANCED (06h-E0h). In this situation, using the CHANGE READ COLUMN ENHANCED (06h-E0h) command without the READ STATUS ENHANCED (78h) command will result in bus contention, as two or more die (LUNs) could output data. If there is a need to update the column address without selecting a new cache register or LUN, the CHANGE READ COLUMN (05h-E0h) command can be used instead. Figure 48: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation
Cycle type DQ[7:0]
Dout
Dout
Command
tRHW
Address
Address
Address
Address
Address
Command
tCCS
Dout
Dout
Dout
Dn
Dn + 1
06h
C1
C2
R1
R2
R3
E0h
Dk
Dk + 1
Dk + 2
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Column Address Operations CHANGE WRITE COLUMN (85h)
The CHANGE WRITE COLUMN (85h) command changes the column address of the selected cache register and enables data input on the last-selected die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache program operations (RDY = 1; ARDY = 0). Writing 85h to the command register, followed by two column address cycles containing the column address, puts the selected die (LUN) into data input mode. After the second address cycle is issued, the host must wait at least tCCS before inputting data. The selected die (LUN) stays in data input mode until another valid command is issued. Though data input mode is enabled, data input from the host is optional. Data input begins at the column address specified. The CHANGE WRITE COLUMN (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), COPYBACK PROGRAM (85h-10h), and COPYBACK PROGRAM MULTI-PLANE (85h-11h). In devices that have more than one die (LUN) per target, the CHANGE WRITE COLUMN (85h) command can be used with other commands that support interleaved die (multi-LUN) operations. Figure 49: CHANGE WRITE COLUMN (85h) Operation
As defined for PAGE (CACHE) PROGRAM As defined for PAGE (CACHE) PROGRAM Command Address Address
tCCS
Cycle type
DIN
DIN
DIN
DIN
DIN
DQ[7:0]
Dn
Dn + 1
85h
C1
C2
Dk
Dk + 1
Dk + 2
RDY
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Column Address Operations CHANGE ROW ADDRESS (85h)
The CHANGE ROW ADDRESS (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address of the selected cache register and enables data input on the specified die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache programming operations (RDY = 1; ARDY = 0). Write 85h to the command register. Then write two column address cycles and three row address cycles. This updates the page and block destination of the selected plane for the addressed LUN and puts the cache register into data input mode. After the fifth address cycle is issued the host must wait at least tCCS before inputting data. The selected LUN stays in data input mode until another valid command is issued. Though data input mode is enabled, data input from the host is optional. Data input begins at the column address specified. The CHANGE ROW ADDRESS (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), COPYBACK PROGRAM (85h-10h), and COPYBACK PROGRAM MULTI-PLANE (85h-11h). When used with these commands, the LUN address and plane select bits are required to be identical to the LUN address and plane select bits originally specified. The CHANGE ROW ADDRESS (85h) command enables the host to modify the original page and block address for the data in the cache register to a new page and block address. In devices that have more than one die (LUN) per target, the CHANGE ROW ADDRESS (85h) command can be used with other commands that support interleaved die (multiLUN) operations. The CHANGE ROW ADDRESS (85h) command can be used with the CHANGE READ COLUMN (05h-E0h) or CHANGE READ COLUMN ENHANCED (06h-E0h) commands to read and modify cache register contents in small sections prior to programming cache register contents to the NAND Flash array. This capability can reduce the amount of buffer memory used in the host controller. To modify the cache register contents in small sections, first issue a PAGE READ (00h-30h) or COPYBACK READ (00h-35h) operation. When data output is enabled, the host can output a portion of the cache register contents. To modify the cache register contents, issue the 85h command, the column and row addresses, and input the new data. The host can re-enable data output by issuing the 11h command, waiting tDBSY, and then issuing the CHANGE READ COLUMN (05h-E0h) or CHANGE READ COLUMN ENHANCED (06h-E0h) command. It is possible toggle between data output and data input multiple times. After the final CHANGE ROW ADDRESS (85h) operation is complete, issue the 10h command to program the cache register to the NAND Flash array.
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Figure 50: CHANGE ROW ADDRESS (85h) Operation
As defined for PAGE (CACHE) PROGRAM As defined for PAGE (CACHE) PROGRAM Command Address Address Address Address Address
tCCS
Cycle type
DIN
DIN
DIN
DIN
DIN
DQ[7:0]
Dn
Dn + 1
85h
C1
C2
R1
R2
R3
Dk
Dk + 1
Dk + 2
RDY
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Read Operations
Read operations are used to copy data from the NAND Flash array of one or more of the planes to their respective cache registers and to enable data output from the cache registers to the host through the DQ bus. Read Operations The READ PAGE (00h-30h) command, when issued by itself, reads one page from the NAND Flash array to its cache register and enables data output for that cache register. During data output the following commands can be used to read and modify the data in the cache registers: CHANGE READ COLUMN (05h-E0h) and CHANGE ROW ADDRESS (85h). Read Cache Operations To increase data throughput, the READ PAGE CACHE-series (31h, 00h-31h) commands can be used to output data from the cache register while concurrently copying a page from the NAND Flash array to the data register. To begin a read page cache sequence, begin by reading a page from the NAND Flash array to its corresponding cache register using the READ PAGE (00h-30h) command. R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands: * READ PAGE CACHE SEQUENTIAL (31h)--copies the next sequential page from the NAND Flash array to the data register * READ PAGE CACHE RANDOM (00h-31h)--copies the page specified in this command from the NAND Flash array (any plane) to its corresponding data register After the READ PAGE CACHE-series (31h, 00h-31h) command has been issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the next page begins copying data from the array to the data register. After tRCBSY, R/B# goes HIGH and the die's (LUN's) status register bits indicate the device is busy with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and the page requested in the READ PAGE CACHE operation is transferred to the data register. At this point, data can be output from the cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data output by the die (LUN). After outputting the desired number of bytes from the cache register, either an additional READ PAGE CACHE-series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST (3Fh) command can be issued. If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready. Data can then be output from the cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output. For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid commands during READ PAGE CACHE-series (31h, 00h-31h) operations are status opera-
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tions (70h, 78h), READ MODE (00h), READ PAGE CACHE-series (31h, 00h-31h), CHANGE READ COLUMN (05h-E0h), and RESET (FFh, FCh). Multi-Plane Read Operations Multi-plane read page operations improve data throughput by copying data from more than one plane simultaneously to the specified cache registers. This is done by prepending one or more READ PAGE MULTI-PLANE (00h-32h) commands in front of the READ PAGE (00h-30h) command. When the die (LUN) is ready, the CHANGE READ COLUMN ENHANCED (06h-E0h) command determines which plane outputs data. During data output, the following commands can be used to read and modify the data in the cache registers: CHANGE READ COLUMN (05h-E0h) and CHANGE ROW ADDRESS (85h). See Multi-Plane Operations for details. Multi-Plane Read Cache Operations Multi-plane read cache operations can be used to output data from more than one cache register while concurrently copying one or more pages from the NAND Flash array to the data register. This is done by prepending READ PAGE MULTI-PLANE (00h-32h) commands in front of the PAGE READ CACHE RANDOM (00h-31h) command. To begin a multi-plane read page cache sequence, begin by issuing a MULTI-PLANE READ PAGE operation using the READ PAGE MULTI-PLANE (00h-32h) and READ PAGE (00h-30h) commands. R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands: * READ PAGE CACHE SEQUENTIAL (31h)--copies the next sequential page from the previously addressed planes from the NAND Flash array to the data registers. * READ PAGE MULTI-PLANE (00h-32h) commands, if desired, followed by the READ PAGE CACHE RANDOM (00h-31h) command--copies the pages specified from the NAND Flash array to the corresponding data registers. After the READ PAGE CACHE-series (31h, 00h-31h) command has been issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the next pages begin copying data from the array to the data registers. After tRCBSY, R/B# goes HIGH and the LUN's status register bits indicate the device is busy with a cache operation (RDY = 1, ARDY = 0). The cache registers become available and the pages requested in the READ PAGE CACHE operation are transferred to the data registers. Issue the CHANGE READ COLUMN ENHANCED (06h-E0h) command to determine which cache register will output data. After data is output, the CHANGE READ COLUMN ENHANCED (06h-E0h) command can be used to output data from other cache registers. After a cache register has been selected, the CHANGE READ COLUMN (05hE0h) command can be used to change the column address of the data output. After outputting data from the cache registers, either an additional MULTI-PLANE READ CACHE-series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST (3Fh) command can be issued.
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If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data registers are copied into the cache registers. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1, indicating that the cache registers are available and that the die (LUN) is ready. Issue the CHANGE READ COLUMN ENHANCED (06h-E0h) command to determine which
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cache register will output data. After data is output, the CHANGE READ COLUMN ENHANCED (06h-E0h) command can be used to output data from other cache registers. After a cache register has been selected, the CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data output. For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid commands during READ PAGE CACHE-series (31h, 00h-31h) operations are status operations (70h, 78h), READ MODE (00h), multi-plane read cache-series (31h, 00h-32h, 00h-31h), CHANGE READ COLUMN (05h-E0h, 06h-E0h), and RESET (FFh, FCh). See Multi-Plane Operations for additional multi-plane addressing requirements.
READ MODE (00h)
The READ MODE (00h) command disables status output and enables data output for the last-selected die (LUN) and cache register after a READ operation (00h-30h, 00h-35h) has been monitored with a status operation (70h, 78h). This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 3Fh, 00h-31h) operations (RDY = 1 and ARDY = 0). In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) prior to issuing the READ MODE (00h) command. This prevents bus contention.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Read Operations READ PAGE (00h-30h)
The READ PAGE (00h-30h) command copies a page from the NAND Flash array to its respective cache register and enables data output. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To read a page from the NAND Flash array, write the 00h command to the command register, the write five address cycles to the address registers, and conclude with the 30h command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is transferred. To determine the progress of the data transfer, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. If the status operations are used to monitor the LUN's status, when the die (LUN) is ready (RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing the READ MODE (00h) command. When the host requests data output, output begins at the column address specified. During data output the CHANGE READ COLUMN (05h-E0h) command can be issued. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) prior to the issue of the READ MODE (00h) command. This prevents bus contention. The READ PAGE (00h-30h) command is used as the final command of a multi-plane read operation. It is preceded by one or more READ PAGE MULTI-PLANE (00h-32h) commands. Data is transferred from the NAND Flash array for all of the addressed planes to their respective cache registers. When the die (LUN) is ready (RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the plane addressed in the READ PAGE (00h-30h) command. When the host requests data output, output begins at the column address last specified in the READ PAGE (00h-30h) command. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to enable data output in the other cache registers. See Multi-Plane Operations for additional multi-plane addressing requirements. Figure 51: READ PAGE (00h-30h) Operation
Cycle type
Command Address Address Address Address Address Command Dout Dout Dout
DQ[7:0]
00h
C1
C2
R1
R2
R3
30h tWB tR tRR
Dn
Dn+1
Dn+2
RDY
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Read Operations READ PAGE CACHE SEQUENTIAL (31h)
The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue this command, write 31h to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register. The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the last page of a block is read into the data register, the next page read will be the next logical block in the plane which the 31h command was issued. Do not issue the READ PAGE CACHE SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE CACHE LAST (3Fh) command. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after a MULTIPLANE READ PAGE operation (00h-32h, 00h-30h), the next sequential pages are read into the data registers while the previous pages can be output from the cache registers. After the die (LUN) is ready (RDY = 1, ARDY = 0), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select which cache register outputs data. Figure 52: READ PAGE CACHE SEQUENTIAL (31h) Operation
Cycle type Command
Address x5
Command
Command
DOUT
DOUT
DOUT
Command
DOUT
DQ[7:0]
00h
Page Address M
30h tWB tR
31h tWB tRCBSY tRR
D0
...
Dn
31h tWB tRCBSY tRR
D0
RDY Page M Page M+1
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Read Operations READ PAGE CACHE RANDOM (00h-31h)
The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and page into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue this command, write 00h to the command register, then write five address cycles to the address register, and conclude by writing 31h to the command register. The column address in the address specified is ignored. The die (LUN) address must match the same die (LUN) address as the previous READ PAGE (00h-30h) command or, if applicable, the previous READ PAGE CACHE RANDOM (00h-31h) command. There is no restriction on the plane address. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by the READ MODE (00h) command must be used to select only one die (LUN) and prevent bus contention. If a MULTI-PLANE CACHE RANDOM (00h-32h, 00h-31h) command is issued after a MULTI-PLANE READ PAGE operation (00h-32h, 00h-30h), then the addressed pages are read into the data registers while the previous pages can be output from the cache registers. After the die (LUN) is ready (RDY = 1, ARDY = 0), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select which cache register outputs data.
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Figure 53: READ PAGE CACHE RANDOM (00h-31h) Operation
Cycle type Command
Address x5
Command
Command
Address x5
Command
DOUT
DOUT
DOUT
Command
DQ[7:0]
00h
Page Address M
30h tWB tR
00h
Page Address N
31h tWB tRCBSY tRR
D0
...
Dn
00h
RDY Page M 1 Cycle type
DOUT Command Address x5 Command DOUT
DQ[7:0]
Dn
00h
Page Address P
31h tWB tRCBSY tRR
D0
RDY Page N 1
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Read Operations READ PAGE CACHE LAST (3Fh)
The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and copies a page from the data register to the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register. In devices that have more than one LUN per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by the READ MODE (00h) command must be used to select only one die (LUN) and prevent bus contention. If the READ PAGE CACHE LAST (3Fh) command is issued after a MULTI-PLANE READ PAGE CACHE operation (31h; 00h-32h, 00h-30h), the die (LUN) goes busy until the pages are copied from the data registers to the cache registers. After the die (LUN) is ready (RDY = 1, ARDY = 1), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select which cache register outputs data. Figure 54: READ PAGE CACHE LAST (3Fh) Operation
As defined for READ PAGE CACHE (SEQUENTIAL OR RANDOM)
Cycle type
Command
DOUT
DOUT
DOUT
Command
DOUT
DOUT
DOUT
DQ[7:0]
31h tWB tRCBSY tRR
D0
...
Dn
3Fh tWB tRCBSY tRR
D0
...
Dn
RDY
Page Address N Page N
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Read Operations READ PAGE MULTI-PLANE (00h-32h)
The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to transfer data from the NAND flash array to its cache register. This command can be issued one or more times. Each time a new plane address is specified, that plane is also queued for data transfer. The READ PAGE (00h-30h) command is issued to select the final plane and to begin the read operation for all previously queued planes. All queued planes will transfer data from the NAND Flash array to their cache registers. To issue the READ PAGE MULTI-PLANE (00h-32h) command, write 00h to the command register, then write five address cycles to the address register, and conclude by writing 32h to the command register. The column address in the address specified is ignored. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tDBSY. After tDBSY, R/B# goes HIGH and the die (LUN) is ready (RDY = 1, ARDY = 1). At this point, the die (LUN) and block are queued for data transfer from the array to the cache register for the addressed plane. During tDBSY, the only valid commands are status operations (70h, 78h) and reset commands (FFh, FCh). Following tDBSY, to continue the MULTI-PLANE READ operation, the only valid commands are status operations (70h, 78h), READ PAGE MULTI-PLANE (00h-32h), READ PAGE (00h-30h), and READ PAGE CACHE RANDOM (00h-31h). Additional READ PAGE MULTI-PLANE (00h-32h) commands can be issued to queue additional planes for data transfer. If the READ PAGE (00h-30h) command is used as the final command of a MULTIPLANE READ operation, data is transferred from the NAND Flash array for all of the addressed planes to their respective cache registers. When the die (LUN) is ready (RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the plane addressed in the READ PAGE (00h-30h) command. When the host requests data output, it begins at the column address specified in the READ PAGE (00h-30h) command. To enable data output in the other cache registers, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READ COLUMN (05h-E0h) command can be used to change the column address within the currently selected plane. If the READ PAGE CACHE SEQUENTIAL (31h) is used as the final command of a MULTIPLANE READ CACHE operation, data is copied from the previously read operation from each plane to each cache register and then data is transferred from the NAND Flash array for all previously addressed planes to their respective data registers. When the die (LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to determine which cache register outputs data first. To enable data output in the other cache registers, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READ COLUMN (05h-E0h) command can be used to change the column address within the currently selected plane. If the READ PAGE CACHE RANDOM (00h-31h) command is used as the final command of a MULTI-PLANE READ CACHE operation, data is copied from the previously read operation from the data register to the cache register and then data is transferred from the NAND Flash array for all of the addressed planes to their respective data registers. When the die (LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to determine which cache register outputs data first. To enable data output in the other cache registers, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command. Additionally, the 87
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CHANGE READ COLUMN (05h-E0h) command can be used to change the column address within the currently selected plane. See Multi-Plane Operations for additional multi-plane addressing requirements. Figure 55: READ PAGE MULTI-PLANE (00h-32h) Operation
Cycle type
Command Address Address Address Address Address Command Command Address Address
DQ[7:0]
00h
C1
C2
R1
R2
R3
32h tWB tDBSY
00h
C1
...
RDY
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Program Operations
Program Operations
Program operations are used to move data from the cache or data registers to the NAND array of one or more planes. During a program operation the contents of the cache and/or data registers are modified by the internal control logic. Within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (i.e. 0, 1, 2, 3, ...). Programming pages out of order within a block is prohibited. Program Operations The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE MULTI-PLANE (80h-11h) command, programs one page from the cache register to the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that the operation has completed successfully. Program Cache Operations The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program operation system performance. When this command is issued, the die (LUN) goes busy (RDY = 0, ARDY = 0) while the cache register contents are copied to the data register, and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0. While the contents of the data register are moved to the NAND Flash array, the cache register is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) command. For PROGRAM PAGE CACHE-series (80h-15h) operations, during the die (LUN) busy times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and reset (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid commands during PROGRAM PAGE CACHE-series (80h-15h) operations are status operations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h), CHANGE WRITE COLUMN (85h), CHANGE ROW ADDRESS (85h), and reset (FFh, FCh). Multi-Plane Program Operations The PROGRAM PAGE MULTI-PLANE (80h-11h) command can be used to improve program operation system performance by enabling multiple pages to be moved from the cache registers to different planes of the NAND Flash array. This is done by prepending one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands in front of the PROGRAM PAGE (80h-10h) command. See Multi-Plane Operations for details. Multi-Plane Program Cache Operations The PROGRAM PAGE MULTI-PLANE (80h-11h) command can be used to improve program cache operation system performance by enabling multiple pages to be moved from the cache registers to the data registers and, while the pages are being transferred from the data registers to different planes of the NAND Flash array, free the cache registers to receive data input from the host. This is done by prepending one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands in front of the PROGRAM PAGE CACHE (80h-15h) command. See Multi-Plane Operations for details.
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PROGRAM PAGE (80h-10h)
The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page ad-
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dress in the array of the selected die (LUN). This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0). To input a page to the cache register and move it to the NAND array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write five address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the CHANGE WRITE COLUMN (85h) and CHANGE ROW ADDRESS (85h) commands may be issued. When data input is complete, write 10h to the command register. The selected LUN will go busy (RDY = 0, ARDY = 0) for tPROG as data is transferred. To determine the progress of the data transfer, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) may be used. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The PROGRAM PAGE (80h-10h) command is used as the final command of a multiplane program operation. It is preceded by one or more PROGRAM PAGE MULTIPLANE (80h-11h) commands. Data is transferred from the cache registers for all of the addressed planes to the NAND array. The host should check the status of the operation by using the status operations (70h, 78h). See Multi-Plane Operations for multi-plane addressing requirements. Figure 56: PROGRAM PAGE (80h-10h) Operation
Cycle type
Command
Address
Address
Address
Address
Address tADL
Din
Din
Din
Din
Command
Command
Dout
DQ[7:0]
80h
C1
C2
R1
R2
R3
D0
D1
...
Dn
10h tWB tPROG
70h
Status
RDY
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Program Operations PROGRAM PAGE CACHE (80h-15h)
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a cache register; copies the data from the cache register to the data register; then moves the data register contents to the specified block and page address in the array of the selected die (LUN). After the data is copied to the data register, the cache register is available for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die (LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0). To input a page to the cache register to move it to the NAND array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write five address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the CHANGE WRITE COLUMN (85h) and CHANGE ROW ADDRESS (85h) commands may be issued. When data input is complete, write 15h to the command register. The selected LUN will go busy (RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a previous program cache operation, to copy data from the cache register to the data register, and then to begin moving the data register contents to the specified page and block address. To determine the progress of tCBSY, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should check the status of the FAILC bit to see if a previous cache operation was successful. If, after tCBSY, the host wants to wait for the program cache operation to complete, without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor ARDY until it is 1. The host should then check the status of the FAIL and FAILC bits. In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a multi-plane program cache operation. It is preceded by one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands. Data for all of the addressed planes is transferred from the cache registers to the corresponding data registers, then moved to the NAND Flash array. The host should check the status of the operation by using the status operations (70h, 78h). See Multi-Plane Operations for multi-plane addressing requirements.
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Figure 57: PROGRAM PAGE CACHE (80h-15h) Operation (Start)
Cycle type
Command
Address
Address
Address
Address
Address tADL
Din
Din
Din
Din
Command
DQ[7:0]
80h
C1
C2
R1
R2
R3
D0
D1
...
Dn
15h tWB tCBSY
RDY
1 Cycle type DQ[7:0]
Command Address Address Address Address Address tADL 80h C1 C2 R1 R2 R3 D0 D1 ... Dn 15h tWB tCBSY Din Din Din Din Command
RDY
1
Figure 58: PROGRAM PAGE CACHE (80h-15h) Operation (End)
As defined for PAGE CACHE PROGRAM
Cycle type
Command
Address
Address
Address
Address
Address tADL
Din
Din
Din
Din
Command
DQ[7:0]
80h
C1
C2
R1
R2
R3
D0
D1
...
Dn
15h tWB tCBSY
RDY
1 Cycle type
Command Address Address Address Address Address tADL Din Din Din Din Command
DQ[7:0]
80h
C1
C2
R1
R2
R3
D0
D1
...
Dn
10h tWB tLPROG
RDY
1
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Program Operations PROGRAM PAGE MULTI-PLANE 80h-11h
The PROGRAM PAGE MULTI-PLANE (80h-11h) command enables the host to input data to the addressed plane's cache register and queue the cache register to ultimately be moved to the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified that plane is also queued for data transfer. To input data for the final plane and to begin the program operation for all previously queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAM PAGE CACHE (80h-15h) command. All of the queued planes will move the data to the NAND Flash array. This command is accepted by the die (LUN) when it is ready (RDY = 1). To input a page to the cache register and queue it to be moved to the NAND Flash array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Write five address cycles containing the column address and row address; data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle, the CHANGE WRITE COLUMN (85h) and CHANGE ROW ADDRESS (85h) commands can be issued. When data input is complete, write 11h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tDBSY. To determine the progress of tDBSY, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows that it is ready (RDY = 1), additional PROGRAM PAGE MULTI-PLANE (80h-11h) commands can be issued to queue additional planes for data transfer. Alternatively, the PROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be issued. When the PROGRAM PAGE (80h-10h) command is used as the final command of a multiplane program operation, data is transferred from the cache registers to the NAND Flash array for all of the addressed planes during tPROG. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of the planes to verify that programming completed successfully. When the PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a MULTI-PLANE PROGRAM CACHE operation, data is transferred from the cache registers to the data registers after the previous array operations finish. The data is then moved from the data registers to the NAND Flash array for all of the addressed planes. This occurs during tCBSY. After tCBSY, the host should check the status of the FAILC bit for each of the planes from the previous program cache operation, if any, to verify that programming completed successfully. For the PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and PROGRAM PAGE CACHE (80h-15h) commands, see Multi-Plane Operations for multiplane addressing requirements.
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Figure 59: PROGRAM PAGE MULTI-PLANE (80h-11h) Operation
Cycle type
Command
Address
Address
Address
Address
Address tADL
Din
Din
Din
Command
Command
Address
DQ[7:0]
80h
C1
C2
R1
R2
R3
D0
...
Dn
11h tWB tDBSY
80h
...
RDY
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Erase Operations
Erase Operations
Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. Erase Operations The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK MULTI-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully. MULTI-PLANE ERASE Operations The ERASE BLOCK MULTI-PLANE (60h-D1h) command can be used to further system performance of erase operations by allowing more than one block to be erased in the NAND array. This is done by prepending one or more ERASE BLOCK MULTI-PLANE (60hD1h) commands in front of the ERASE BLOCK (60h-D0h) command. See Multi-Plane Operations for details.
ERASE BLOCK (60h-D0h)
The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To erase a block, write 60h to the command register. Then write three address cycles containing the row address; the page address is ignored. Conclude by writing D0h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERS while the block is erased. To determine the progress of an ERASE operation, the host can monitor the target's R/ B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die (LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The ERASE BLOCK (60h-D0h) command is used as the final command of a MULTIPLANE ERASE operation. It is preceded by one or more ERASE BLOCK MULTI-PLANE (60h-D1h) commands. All of blocks in the addressed planes are erased. The host should check the status of the operation by using the status operations (70h, 78h). See MultiPlane Operations for multi-plane addressing requirements. Figure 60: ERASE BLOCK (60h-D0h) Operation
Cycle type
Command Address Address Address Command
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DQ[7:0] SR[6]
60h R1 R2 R3 D0h
tWB tBERS
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Erase Operations ERASE BLOCK MULTI-PLANE (60h-D1h)
The ERASE BLOCK MULTI-PLANE (60h-D1h) command queues a block in the specified plane to be erased in the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified, that plane is also queued for a block to be erased. To specify the final block to be erased and to begin the ERASE operation for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To queue a block to be erased, write 60h to the command register, then write three address cycles containing the row address; the page address is ignored. Conclude by writing D1h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tDBSY. To determine the progress of tDBSY, the host can monitor the target's R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows that it is ready (RDY = 1, ARDY = 1), additional ERASE BLOCK MULTI-PLANE (60hD1h) commands can be issued to queue additional planes for erase. Alternatively, the ERASE BLOCK (60h-D0h) command can be issued to erase all of the queued blocks. For multi-plane addressing requirements for the ERASE BLOCK MULTI-PLANE (60hD1h) and ERASE BLOCK (60h-D0h) commands, see Multi-Plane Operations. Figure 61: ERASE BLOCK MULTI-PLANE (60h-D1h) Operation
Cycle type
Command Address Address Address Command Command Address
DQ[7:0] RDY
60h
R1
R2
R3
D1h
tWB tDBSY
60h
...
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Copyback Operations
Copyback Operations
COPYBACK operations make it possible to transfer data within a plane from one page to another using the cache register. This is particularly useful for block management and wear leveling. The COPYBACK operation is a two-step process consisting of a COPYBACK READ (00h-35h) and a COPYBACK PROGRAM (85h-10h) command. To move data from one page to another on the same plane, first issue the COPYBACK READ (00h-35h) command. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host can transfer the data to a new page by issuing the COPYBACK PROGRAM (85h-10h) command. When the die (LUN) is again ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully. To prevent bit errors from accumulating over multiple COPYBACK operations, it is recommended that the host read the data out of the cache register after the COPYBACK READ (00h-35h) completes prior to issuing the COPYBACK PROGRAM (85h-10h) command. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address. The host should check the data for ECC errors and correct them. When the COPYBACK PROGRAM (85h-10h) command is issued, any corrected data can be input. The CHANGE ROW ADDRESS (85h) command can be used to change the column address. It is not possible to use the COPYBACK operation to move data from one plane to another or from one die (LUN) to another. Instead, use a READ PAGE (00h-30h) or COPYBACK READ (00h-35h) command to read the data out of the NAND, and then use a PROGRAM PAGE (80h-10h) command with data input to program the data to a new plane or die (LUN). Between the COPYBACK READ (00h-35h) and COPYBACK PROGRAM (85h-10h) commands, the following commands are supported: status operations (70h, 78h), and column address operations (05h-E0h, 06h-E0h, 85h). Reset operations (FFh, FCh) can be issued after COPYBACK READ (00h-35h), but the contents of the cache registers on the target are not valid. In devices which have more than one die (LUN) per target, once the COPYBACK READ (00h-35h) is issued, interleaved die (multi-LUN) operations are prohibited until after the COPYBACK PROGRAM (85h-10h) command is issued. Multi-Plane Copyback Operations Multi-plane copyback read operations improve read data throughput by copying data simultaneously from more than one plane to the specified cache registers. This is done by prepending one or more READ PAGE MULTI-PLANE (00h-32h) commands in front of the COPYBACK READ (00h-35h) command. The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command can be used to further system performance of COPYBACK PROGRAM operations by enabling movement of multiple pages from the cache registers to different planes of the NAND Flash array. This is done by prepending one or more COPYBACK PROGRAM (85h-11h) commands in front of the COPYBACK PROGRAM (85h-10h) command. See Multi-Plane Operations for details.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Copyback Operations COPYBACK READ (00h-35h)
The COPYBACK READ (00h-35h) command is functionally identical to the READ PAGE (00h-30h) command, except that 35h is written to the command register instead of 30h. See READ PAGE (00h-30h) (page 82) for further details. Though it is not required, it is recommended that the host read the data out of the device to verify the data prior to issuing the COPYBACK PROGRAM (85h-10h) command to prevent the propagation of data errors. Figure 62: COPYBACK READ (00h-35h) Operation
Cycle type
Command Address Address Address Address Address Command DOUT DOUT DOUT
DQ[7:0] RDY
00h
C1
C2
R1
R2
R3
35h
tWB tR tRR
Dn
Dn+1
Dn+2
Figure 63: COPYBACK READ (00h-35h) with CHANGE READ COLUMN (05h-E0h) Operation
Cycle type
Command
Address
Address
Address
Address
Address
Command
DOUT
DOUT
DOUT
DQ[7:0] RDY
00h
C1
C2
R1
R2
R3
35h
tWB tR tRR
D0
...
Dj + n
1 Cycle type
Command Address Address Command
tCCS
DOUT
DOUT
DOUT
DQ[7:0] RDY
05h
C1
C2
E0h
Dk
Dk + 1
Dk + 2
1
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Copyback Operations COPYBACK PROGRAM (85h-10h)
The COPYBACK PROGRAM (85h-10h) command is functionally identical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. See PROGRAM PAGE (80h-10h) (page 89) for further details. Figure 64: COPYBACK PROGRAM (85h-10h) Operation
Cycle type
Command Address Address Address Address Address Command
DQ[7:0] RDY
85h
C1
C2
R1
R2
R3
10h
tWB tPROG
Figure 65: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation
Cycle type
Command
Address
Address
Address
Address
Address
tADL
DIN
DIN
DQ[7:0] RDY
85h
C1
C2
R1
R2
R3
Di
Di + 1
1 Cycle type
Command Address Address
tCCS
DIN
DIN
DIN
Command
DQ[7:0] RDY
85h
C1
C2
Dj
Dj + 1
Dj + 2
10h
tWB tPROG
1
COPYBACK READ MULTI-PLANE (00h-32h)
The COPYBACK READ MULTI-PLANE (00h-32h) command is functionally identical to the READ PAGE MULTI-PLANE (00h-32h) command, except that the 35h command is written as the final command. The complete command sequence for the COPYBACK READ PAGE MULTI-PLANE is 00h-32h-00h-35h. See READ PAGE MULTI-PLANE (00h-32h) (page 87) for further details.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Copyback Operations COPYBACK PROGRAM MULTI-PLANE (85h-11h)
The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command is functionally identical to the PROGRAM PAGE MULTI-PLANE (80h-11h) command, except that when 85h is written to the command register, cache register contents are not cleared. See PROGRAM PAGE MULTI-PLANE 80h-11h (page 93) for further details. Figure 66: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation
Cycle type
Command
Address
Address
Address
Address
Address
tADL
DIN
DIN
DIN
Command
Command
Address
DQ[7:0] RDY
85h
C1
C2
R1
R2
R3
D0
...
Dn
11h
tWB tDBSY
85h
...
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) Operations
One-Time Programmable (OTP) Operations
This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Each target has a an OTP area with a range of OTP pages (see Table 15 (page 102)); the entire range is guaranteed to be good. Customers can use the OTP area in any way they desire; typical uses include programming serial numbers or other data for permanent storage. The OTP area leaves the factory in an erased state (all bits are 1). Programming an OTP page changes bits that are 1 to 0, but cannot change bits that are 0 to 1. The OTP area cannot be erased, even if it is not protected. Protecting the OTP area prevents further programming of the pages in the OTP area. Enabling the OTP Operation Mode The OTP area is accessible while the OTP operation mode is enabled. To enable OTP operation mode, issue the SET FEATURES (EFh) command to feature address 90h and write 01h to P1, followed by three cycles of 00h to P2 through P4. When the target is in OTP operation mode, all subsequent PAGE READ (00h-30h) and PROGRAM PAGE (80h-10h) commands are applied to the OTP area. ERASE commands are not valid while the target is in OTP operation mode. Programming OTP Pages Each page in the OTP area is programming using tthe PROGRAM OTP PAGE (80h-10h) command. Each page can be programmed more than once, in sections, up to the maximum number allowed (see NOP in Table 15 (page 102)). The pages in the OTP area must be programmed in ascending order. If the host issues a PAGE PROGRAM (80h-10h) command to an address beyond the maximum page-address range, the target will be busy for tOBSY and the WP# status register bit will be 0, meaning that the page is write-protected. Protecting the OTP Area To protect the OTP area, issue the OTP PROTECT (80h-10h) command to the OTP Protect Page. When the OTP area is protected it cannot be programmed further. It is not possible to unprotect the OTP area after it has been protected. Reading OTP Pages To read pages in the OTP area, whether the OTP area is protected or not, issue the PAGE READ (00h-30h) command. If the host issues the PAGE READ (00h-30h) command to an address beyond the maximum page-address range, the data output will not be valid. To determine whether the target is busy during an OTP operation, either monitor R/B# or use the READ STATUS (70h) command. Use of the READ STATUS ENHANCED (78h) command is prohibited while the OTP operation is in progress.
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Returning to Normal Array Operation Mode To exit OTP operation mode and return to normal array operation mode, issue the SET FEATURES (EFh) command to feature address 90h and write 00h to P1 through P4. If the RESET (FFh) command is issued while in OTP operation mode, the target will exit OTP operation mode and enter normal operating mode. If the synchronous interface is active, the target will exit OTP operation and enable the asynchronous interface.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) Operations
If the SYNCHRONOUS RESET (FCh) command is issued while in the OTP operation mode, the target will exit OTP operation mode and the synchronous interface remains active. Table 15: OTP Area Details
Description Number of OTP pages OTP protect page address OTP start page address Number of partial page programs (NOP) to each OTP page Value 30 01h 02h 8
PROGRAM OTP PAGE (80h-10h)
The PROGRAM OTP PAGE (80h-10h) command is used to write data to the pages within the OTP area. To program data in the OTP area, the target must be in OTP operation mode. To use the PROGRAM OTP PAGE (80h-10h) command, issue the 80h command. Issue five address cycles including the column address, the page address within the OTP page range, and a block address of 0. Next, write the data to the cache register using data input cycles. After data input is complete, issue the 10h command. R/B# goes LOW for the duration of the array programming time, tPROG. The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ STATUS ENHANCED (78h) command is prohibited. When the target is ready, read the FAIL bit of the status register to determine whether the operation passed or failed (see Table 14 (page 71)). The PROGRAM OTP PAGE (80h-10h) command also accepts the CHANGE WRITE COLUMN (85h) command during data input. If a PROGRAM PAGE command is issued to the OTP area after the area has been protected, then R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h. Figure 67: PROGRAM OTP PAGE (80h-10h) Operation
Cycle type
Command Address Address Address Address Address tADL Din Din Din Command Command tWHR D1 ... Dn 10h tWB tPROG 70h Status Dout
DQ[7:0] R/B#
80h
C1
C2
OTP Page
00h
00h
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) Operations
Figure 68: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation
Cycle type
Command
Address
Address
Address
Address
Address tADL
Din
Din
Din
Command
DQ[7:0] R/B#
80h
C1
C2
OTP Page
00h
00h
Dn
...
Dm
85h
1
Cycle type
Command
Address
Address tCCS
Din
Din
Din
Command
Command tWHR
Dout
DQ[7:0] R/B#
85h
C1
C2
Dp
...
Dr
10h tWB tPROG
70h
Status
1
PROTECT OTP AREA (80h-10h)
The PROTECT OTP AREA (80h-10h) command is used to prevent further programming of the pages in the OTP area. The protect the OTP area, the target must be in OTP operation mode. To protect all data in the OTP area, issue the 80h command. Issue five address cycles including the column address, OTP protect page address and block address; the column and block addresses are fixed to 0. Next, write 00h data for the first byte location and issue the 10h command. R/B# goes LOW for the duration of the array programming time, tPROG. The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ STATUS ENHANCED (78h) command is prohibited. When the target is ready, read the FAIL bit of the status register to determine if the operation passed or failed (see Table 14 (page 71)). If the PROTECT OTP AREA (80h-10h) command is issued after the OTP area has already been protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) Operations
Figure 69: PROTECT OTP AREA (80h-10h) Operation
Cycle type
Command
Address
Address
Address
Address
Address tADL
Din
Command
Command tWHR
Dout
DQ[7:0] R/B#
80h
00h
00h
01h
00h
00h
00h
10h tWB tPROG
70h
Status
Note:
1. OTP data is protected following a status confirmation.
READ OTP PAGE (00h-30h)
The READ OTP PAGE (00h-30h) command is used to read data from the pages in the OTP area. To read data in the OTP area, the target must be in OTP operation mode. To use the READ OTP PAGE (00h-30h) command, issue the 00h command. Issue five address cycles including the column address, the page address within the OTP page range, and a block address of 0. Next, issue the 30h command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is transferred. To determine the progress of the data transfer, the host can monitor the target's R/B# signal, or alternatively the READ STATUS (70h) command can be used. If the status operations are used to monitor the die's (LUN's) status, when the die (LUN) is ready (RDY = 1, ARDY = 1) the host disables status output and enables data output by issuing the READ MODE (00h) command. When the host requests data output, it begins at the column address specified. Additional pages within the OTP area can be read by repeating the READ OTP PAGE (00h-30h) command. The READ OTP PAGE (00h-30h) command is compatible with the CHANGE READ COLUMN (05h-E0h) command. Use of the READ STATUS ENHANCED (78h) and CHANGE READ COLUMN ENHANCED (06h-E0h) commands are prohibited. Figure 70: READ OTP PAGE (00h-30h) Operation
Cycle type
Command Address Address Address Address Address Command Dout Dout Dout
DQ[7:0] R/B#
00h
C1
C2
OTP Page
00h
00h
30h tWB tR tRR
Dn
Dn+1
Dn+2
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Multi-Plane Operations
Multi-Plane Operations
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each plane contains a cache register and a data register independent of the other planes. The planes are addressed via the low-order block address bits. Specific details are provided in Device and Array Organization. Multi-plane operations make better use of the NAND Flash arrays on these physical planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple planes, significantly improving system performance. Multi-plane operations must be of the same type across the planes; for example, it is not possible to perform a PROGRAM operation on one plane with an ERASE operation on another. When issuing MULTI-PLANE PROGRAM or ERASE operations, use the READ STATUS (70h) command and check whether the previous operation(s) failed. If the READ STATUS (70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use the READ STATUS ENHANCED (78h) command--time for each plane--to determine which plane operation failed.
Multi-Plane Addressing
Multi-plane commands require an address per operational plane. For a given multiplane operation, these addresses are subject to the following requirements: * The LUN address bit(s) must be identical for all of the issued addresses. * The plane select bit, BA[7], must be different for each issued address. * The page address bits, PA[6:0], must be identical for each issued address. The READ STATUS (70h) command should be used following MULTI-PLANE PROGRAM PAGE and ERASE BLOCK operations on a single die (LUN).
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Interleaved Die (Multi-LUN) Operations
Interleaved Die (Multi-LUN) Operations
In devices that have more than one die (LUN) per target, it is possible to improve performance by interleaving operations between the die (LUNs). An interleaved die (multiLUN) operation is one that is issued to an idle die (LUN) (RDY = 1) while another die (LUN) is busy (RDY = 0). Interleaved die (multi-LUN) operations are prohibited following RESET (FFh, FCh), identification (90h, ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1 for all of the die (LUNs) on the target. During an interleaved die (multi-LUN) operation, there are two methods to determine operation completion. The R/B# signal indicates when all of the die (LUNs) have finished their operations. R/B# remains LOW while any die (LUN) is busy. When R/B# goes HIGH, all of the die (LUNs) are idle and the operations are complete. Alternatively, the READ STATUS ENHANCED (78h) command can report the status of each die (LUN) individually. If a die (LUN) is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h), then the die (LUN) is able to accept the data for another cache operation when status register bit 6 is 1. All operations, including cache operations, are complete on a die when status register bit 5 is 1. Use the READ STATUS ENHANCED (78h) command to monitor status for the addressed die (LUN). When multi-plane commands are used with interleaved die (multiLUN) operations, the multi-plane commands must also meet the requirements, see MultiPlane Operations for details. After the READ STATUS ENHANCED (78h) command has been issued, the READ STATUS (70h) command may be issued for the previously addressed die (LUN). See Command Definitions for the list of commands that can be issued while other die (LUNs) are busy. During an interleaved die (multi-LUN) operation that involves a PROGRAM-series (80h-10h, 80h-15h, 80h-11h) operation and a READ operation, the PROGRAM-series operation must be issued before the READ-series operation. The data from the READseries operation must be output to the host before the next PROGRAM-series operation is issued. This is because the 80h command clears the cache register contents of all cache registers on all planes.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Error Management
Error Management
Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks (NVB) of the total available blocks. This means the die (LUNs) could have blocks that are invalid when shipped from the factory. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional blocks can develop with use. However, the total number of available blocks per die (LUN) will not fall below NVB during the endurance life of the product. Although NAND Flash memory devices could contain bad blocks, they can be used quite reliably in systems that provide bad-block management and error-correction algorithms. This type of software environment ensures data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array. NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by attempting to program the bad-block mark into every location in the first page of each invalid block. It may not be possible to program every location with the bad-block mark. However, the first spare area location in each bad block is guaranteed to contain the bad-block mark. This method is compliant with ONFI Factory Defect Mapping requirements. See the following table for the first spare area location and the bad-block mark. System software should check the first spare area location on the first page of each block prior to performing any PROGRAM or ERASE operations on the NAND Flash device. A bad block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks could be marginal, it may not be possible to recover this information if the block is erased. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, the following precautions are required: * Always check status after a PROGRAM or ERASE operation * Under typical conditions, use the minimum required ECC (see table below) * Use bad-block management and wear-leveling algorithms The first block (physical block address 00h) for each CE# is guaranteed to be valid with ECC when shipped from the factory. Table 16: Error Management Details
Description Minimum number of valid blocks (NVB) per LUN Total available blocks per LUN First spare area location Requirement 4016 4096 Byte 4096 00h 4-bit ECC per 540 bytes of data
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Bad-block mark Minimum required ECC
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Output Drive Impedance
Output Drive Impedance
Because NAND Flash is designed for use in systems that are typically point-to-point connections, an option to control the drive strength of the output buffers is provided. Drive strength should be selected based on the expected loading of the memory bus. There are four supported settings for the output drivers: overdrive 2, overdrive 1, nominal, and underdrive. The nominal output drive strength setting is the power-on default value. The host can select a different drive strength setting using the SET FEATURES (EFh) command. The output impedance range from minimum to maximum covers process, voltage, and temperature variations. Devices are not guaranteed to be at the nominal line. Table 17: Output Drive Strength Test Conditions (VCCQ = 1.7-1.95V)
Range Maximum Nominal Minimum Process Fast-Fast Typical-Typical Slow-Slow Voltage 1.95V 1.8V 1.7V Temperature -25C +25C +85C
Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7-1.95V)
Output Strength Overdrive 2 Rpd/Rpu Rpd VOUT to VSSQ VCCQ x 0.2 VCCQ x 0.5 VCCQ x 0.8 Rpu VCCQ x 0.2 VCCQ x 0.5 VCCQ x 0.8 Overdrive 1 Rpd VCCQ x 0.2 VCCQ x 0.5 VCCQ x 0.8 Rpu VCCQ x 0.2 VCCQ x 0.5 VCCQ x 0.8 Nominal Rpd VCCQ x 0.2 VCCQ x 0.5 VCCQ x 0.8 Rpu VCCQ x 0.2 VCCQ x 0.5 VCCQ x 0.8 Minimum 7.5 9 11 11 9 7.5 10.5 13 16 16 13 10.5 15 18 22 22 18 15 Nominal 13.5 18 23.5 23.5 18 13.5 19 25 32.5 32.5 25 19 27 35 52 52 35 27 Maximum 34 31 44 44 31 34 47 44 61.5 61.5 44 47 66.5 62.5 88 88 62.5 66.5 Unit ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Output Drive Impedance
Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7-1.95V) (Continued)
Output Strength Underdrive Rpd/Rpu Rpd VOUT to VSSQ VCCQ x 0.2 VCCQ x 0.5 VCCQ x 0.8 Rpu VCCQ x 0.2 VCCQ x 0.5 VCCQ x 0.8 Minimum 21.5 26 31.5 31.5 26 21.5 Nominal 39 50 66.5 66.5 50 39 Maximum 95 90 126.5 126.5 90 95 Unit ohms ohms ohms ohms ohms ohms
Table 19: Output Drive Strength Conditions (VCCQ = 2.7-3.6V)
Range Maximum Nominal Minimum Process Fast-Fast Typical-Typical Slow-Slow Voltage 3.6V 3.3V 2.7V Temperature -40C +25C +85C
Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7-3.6V)
Output Strength Overdrive 2 Rpd/Rpu Rpd VOUT to VSSQ VCCQ X 0.2 VCCQ X 0.5 VCCQ X 0.8 Rpu VCCQ X 0.2 VCCQ X 0.5 VCCQ X 0.8 Overdrive 1 Rpd VCCQ X 0.2 VCCQ X 0.5 VCCQ X 0.8 Rpu VCCQ X 0.2 VCCQ X 0.5 VCCQ X 0.8 Nominal Rpd VCCQ X 0.2 VCCQ X 0.5 VCCQ X 0.8 Minimum 6.0 10.0 15.0 15.0 10.0 6.0 8.0 15.0 20.0 20.0 15.0 8.0 12.0 20.0 25.0 25.0 20.0 12.0 Nominal 10.0 18.0 25.0 25.0 18.0 10.0 15.0 25.0 35.0 35.0 25.0 15.0 22.0 35.0 50.0 50.0 35.0 22.0 Maximum 18.0 35.0 49.0 49.0 35.0 18.0 30.0 45.0 65.0 65.0 45.0 30.0 40.0 65.0 100.0 100.0 65.0 40.0 Unit ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms ohms
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Rpu
VCCQ X 0.2 VCCQ X 0.5 VCCQ X 0.8
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Output Drive Impedance
Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7-3.6V) (Continued)
Output Strength Underdrive Rpd/Rpu Rpd VOUT to VSSQ VCCQ X 0.2 VCCQ X 0.5 VCCQ X 0.8 Rpu VCCQ X 0.2 VCCQ X 0.5 VCCQ X 0.8 Minimum 18.0 29.0 40.0 40.0 29.0 18.0 Nominal 32.0 50.0 75.0 75.0 50.0 32.0 Maximum 55.0 100.0 150.0 150.0 100.0 55.0 Unit ohms ohms ohms ohms ohms ohms
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch
Drive Strength Overdrive 2 Overdrive 1 Nominal Underdrive Notes: Minimum 0 0 0 0 Maximum 6.3 8.8 12.3 17.5 Unit ohms ohms ohms ohms Notes 1, 2 1, 2 1, 2 1, 2
1. Mismatch is the absolute value between pull-up and pull-down impedances. Both are measured at the same temperature and voltage. 2. Test conditions: VCCQ = VCCQ (MIN), VOUT = VCCQ x 0.5, TA = TOPER.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND AC Overshoot/Undershoot Specifications
AC Overshoot/Undershoot Specifications
The supported AC overshoot and undershoot area depends on the timing mode selected by the host. Table 22: Overshoot/Undershoot Parameters
Timing Mode Parameter Maximum peak amplitude provided for overshoot area Maximum peak amplitude provided for undershoot area Maximum overshoot area above VCCQ Maximum undershoot area below VSSQ 0 1 1 3 3 1 1 1 3 3 2 1 1 3 3 3 1 1 2.25 2.25 4 1 1 1.8 1.8 5 1 1 1.5 1.5 Unit V V V-ns V-ns
Figure 71: Overshoot
Volts (V)
Maximum amplitude Overshoot area
VCCQ
Time (ns)
Figure 72: Undershoot
Volts (V)
Maximum amplitude VSSQ
Time (ns)
Undershoot area
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Synchronous Input Slew Rate
Synchronous Input Slew Rate
Though all AC timing parameters are tested with a nominal input slew rate of 1 V/ns, it is possible to run the device at a slower slew rate. The input slew rates shown below are sampled, and not 100% tested. When using slew rates slower than the minimum values, timing must be derated by the host. Table 23: Test Conditions for Input Slew Rate
Parameter Rising edge Falling edge Temperature range Value VIL(DC) To VIH(AC) VIH(DC) To VIL(AC) TA
Table 24: Input Slew Rate (VCCQ = 1.7-1.95V)
CLK/DQS Slew Rate Derating VIH(AC)/VIL(AC)= 540mV, VIH(DC)/VIL(DC)= 360mV Command/ 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Address and DQ V/ns set hold set hold set hold set hold set hold set hold set hold set hold 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 0 0 180 180 360 660 180 360 660 660 920 660 920
Unit ps ps ps ps ps ps ps ps
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Output Slew Rate
Output Slew Rate
The output slew rate is tested using the following setup with only one die per DQ channel. Table 25: Test Conditions for Output Slew Rate
Parameter VOL(DC) VOH(AC) VOL(AC) VOH(DC) Rising edge (tRISE) Falling edge (tFALL) Output capacitive load (CLOAD) Temperature range Value 0.3 x VCCQ 0.7 x VCCQ 0.2 x VCCQ 0.8 x VCCQ VOL(DC) to VOH(AC) VOH(DC) to VOL(AC) 5pF TA
Table 26: Output Slew Rate (VCCQ = 1.7-1.95V)
Output Drive Strength Overdrive 2 Overdrive 1 Nominal Underdrive Min 1 0.85 0.75 0.6 Max 5.5 5 4 4 Unit V/ns V/ns V/ns V/ns
Table 27: Output Slew Rate (VCCQ = 2.7-3.6V)
Output Drive Strength Overdrive 2 Overdrive 1 Nominal Underdrive Min 1.5 1.5 1.2 1.0 Max 10.0 9.0 7.0 5.5 Unit V/ns V/ns V/ns V/ns
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Electrical Specifications
Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods can affect reliability. Table 28: Absolute Maximum Ratings by Device
Parameter Voltage input VCC supply voltage VCCQ supply voltage Storage temperature Note: Symbol VIN VCC VCCQ TSTG Min1 -0.6 -0.6 -0.6 -65 Max1 4.6 4.6 4.6 150 Unit V V V C
1. Voltage on any pin relative to VSS.
Table 29: Recommended Operating Conditions
Parameter Operating temperature VCC supply voltage VCCQ supply voltage (1.8V) VCCQ supply voltage (3.3V) VSS ground voltage VSS Commercial Industrial VCC VCCQ Symbol TA Min 0 -40 2.7 1.7 2.7 0 Typ - - 3.3 1.8 3.3 0 Max 70 +85 3.6 1.95 3.6 0 V V V V Unit C
Table 30: Valid Blocks per LUN
Parameter Valid block number Note: Symbol NVB Min 4016 Max 4096 Unit Blocks Notes 1
1. Invalid blocks are block that contain one or more bad bits beyond ECC. The device may contain bad blocks upon shipment. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked invalid from the factory.
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Electrical Specifications
Table 31: Capacitance: 100-Ball BGA Package
Notes 1 and 2 apply to entire table Single Die/Dual Die Package Description Input capacitance (CLK) Input capacitance (ALE, CLE, W/R#) Input/output capacitance (DQ[7:0], DQS) Input capacitance (CE#, WP#) Delta clock capacitance Delta input capacitance Delta input/output capacitance Symbol CCK CIN CIO Min 3.0 3.5 4 Typ 3.5 4 4.5 Max 4.0 4.5 5 Quad Die Package Min 5.2 5.8 7 Typ 6.2 6.8 8 Max 7.2 7.8 9 Octal Die Package Min 8.5 8.5 12.5 Typ 10.5 10.5 14.5 Max 12.5 12.5 16.5 Unit pF pF pF Notes 3 3 3
COTHER DCCK DCIN DCIO
- - - -
- - - -
5 0.25 0.5 0.5
- - - -
- - - -
10 0.5 1 1
- - - -
- - - -
13 1 2 2
pF pF pF pF
Notes:
1. Verified in device characterization; not 100% tested. 2. Test conditions: TA = 25C, = 100 MHz, VIN = 0V. 3. Values for CCK, CIN and CIO (TYP) are estimates.
Table 32: Capacitance: 48-Pin TSOP Package
Description Input capacitance - ALE, CE#, CLE, RE# (W/R#), WE# (CLK), WP# Input/output capacitance - DQ[7:0], DQS Symbol CIN Device Single die package Dual die package Quad die package CIO Single die package Dual die package Quad die package Note: Max 10 14 18 5 10 18 pF 1 Unit pF Notes 1
1. These parameters are verified in device characterization and are not 100% tested. Test conditions: TC = 25C; f = 1 MHz; Vin = 0V.
Table 33: Capacitance: 52-Pad LGA Package
Description Input capacitance - ALE, CE#, CLE, RE#, www..com WE#, WP# Symbol CIN Device Quad die package Octal die package Max 10 20 Unit pF Notes 1
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Table 33: Capacitance: 52-Pad LGA Package (Continued)
Description Input/output capacitance - DQ[7:0] Symbol CIO Device Quad die package Octal die package Note: Max 14 20 Unit pF Notes 1
1. These parameters are verified in device characterization and are not 100% tested. Test conditions: TC = 25C; f = 1 MHz; Vin = 0V.
Table 34: Test Conditions
Parameter Rising input transition Falling input transition Input rise and fall slew rates Input and output timing levels Output load: Nominal output drive strength Notes: Value VIL(DC) to VIH(AC) VIH(DC) to VIL(AC) 1 V/ns VCCQ/2 CL = 5pF Notes 1 1 - - 2, 3
1. The receiver will effectively switch as a result of the signal crossing the AC input level; it will remain in that status as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. 2. Transmission line delay is assumed to be very small. 3. This test setup applies to all package configurations.
Electrical Specifications - DC Characteristics and Operating Conditions (Asynchronous)
Table 35: DC Characteristics and Operating Conditions (Asynchronous Interface)
Parameter Array read current (active) Array program current (active) Erase current (active) I/O burst read current I/O burst write current Bus idle current Current during first RESET command after power-on Standby current - VCC Standby current - VCCQ www..com Staggered power-up current Note:
tRC tWC
Conditions - - - = tRC (MIN); IOUT= 0mA =
tWC
Symbol ICC1_A ICC2_A ICC3_A ICC4R_A ICC4w_A ICC5_A ICC6 ISB ISBQ IST
Min1 - - - - - - - - - -
Typ1 20 20 20 5 5 3 - 10 3 -
Max1 50 50 50 10 10 5 10 50 10 10
Unit mA mA mA mA mA mA mA A A mA
(MIN)
- - CE# = VCCQ - 0.2V; WP# = 0V/VCCQ CE# = VCCQ - 0.2V; WP# = 0V/VCCQ
tRISE
= 1ms; CLINE = 0.1uF
1. All values are per die (LUN) unless otherwise specified.
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Electrical Specifications - DC Characteristics and Operating Conditions (Synchronous)
Table 36: DC Characteristics and Operating Conditions (Synchronous Interface)
Parameter Array read current (active) Array program current (active) Erase current (active) I/O burst read current I/O burst write current Bus idle current Standby current - VCC Standby Current - VCCQ Note: Conditions CE# = VIL;
tCK tCK tCK tCK tCK tCK
Symbol (MIN) ICC1_S ICC2_S ICC3_S ICC4R_S ICC4W_S ICC5_S ISB ISBQ
Min1 - - - - - - - -
Typ1 20 20 20 10 10 5 10 3
Max1 50 50 50 20 20 10 50 10
Unit mA mA mA mA mA mA A A
=
tCK
= = = =
tCK
(MIN) (MIN) (MIN) (MIN)
= tCK (MIN)
tCK tCK tCK
CE# = VCCQ - 0.2V; WP# = 0V/VCCQ CE# = VCCQ - 0.2V; WP# = 0V/VCCQ
1. All values are per die (LUN) unless otherwise specified.
Electrical Specifications - DC Characteristics and Operating Conditions (VCCQ)
Table 37: DC Characteristics and Operating Conditions (3.3V VCCQ)
Parameter AC input high voltage AC input low voltage DC input high voltage DC input low voltage Input leakage current Output leakage current Output low current (R/B#) Notes: Condition CE#, DQ[7:0], DQS, ALE, CLE, CLK (WE#), W/R# (RE#), WP# DQ[7:0], DQS, ALE, CLE, CLK (WE#), W/R# (RE#) Any input VIN = 0V to VCCQ (all other pins under test = 0V) DQ are disabled; VOUT = 0V to VCCQ VOL = 0.4V Symbol VIH(AC) VIL(AC) VIH(DC) VIL(DC) ILI ILO IOL (R/B#) Min 0.8 x VCCQ -0.3 0.7 x VCCQ -0.3 - - 8 Typ - - - - - - 10 Max VCCQ + 0.3 0.2 x VCCQ VCCQ + 0.3 0.3 x VCCQ 10 10 - Unit V V V V A A mA 1 2 Notes
1. All leakage currents are per die (LUN). Two die (LUNs) have a maximum leakage current of 20A and four die (LUNs) have a maximum leakage current of 40A in the asynchronous interface. 2. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full strength. See Table 14 (page 71) for additional details.
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Table 38: DC Characteristics and Operating Conditions (1.8V VCCQ)
Parameter AC input high voltage AC input low voltage DC input high voltage DC input low voltage Input leakage current Output leakage current Output low current (R/B#) Note: Condition CE#, DQ[7:0], DQS, ALE, CLE, CLK (WE#), W/R# (R/E#), WP# DQ[7:0], DQS, ALE, CLE, CLK (WE#), W/R# (R/E#) Any input VIN = 0V to VCCQ (all other pins under test = 0V) DQ are disabled; Vout = 0V to VCCQ VOL = 0.2V Symbol VIH(AC) VIL(AC) VIH(DC) VIL(DC) ILI ILO IOL (R/B#) Min 0.8 x VCCQ -0.3 0.7 x VCCQ -0.3 - - 3 Typ - - - - - - 4 Max VCCQ + 0.3 0.2 x VCCQ VCCQ + 0.3 0.3 x VCCQ 10 10 - Unit V V V V A A mA 1 1 Notes
1. All leakage currents are per die (LUN). Two die (LUNs) have a maximum leakage current of 20A and four die (LUNs) have a maximum leakage current of 40A in the asynchronous interface.
Electrical Specifications - AC Characteristics and Operating Conditions (Asynchronous)
Table 39: AC Characteristics: Asynchronous Command, Address, and Data
Mode 0 Parameter Clock period Frequency ALE to data start ALE hold time ALE setup time ALE to RE# delay CE# access time Change column setup time to data in/ out or next command CE# hold time CE# HIGH to output High-Z CLE hold time CLE to RE# delay www..com CLE setup time CE# HIGH to output hold CE# setup time Data hold time
tADL tALH tALS tAR tCEA tCCS
Mode 1 50 20
Mode 2 35 28
Mode 3 30 33
Mode 4 25 40
Mode 5 20 50 ns MHz - - - - 25 - ns ns ns ns ns ns 1
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes 100 10 200 20 50 25 - 200 - - - - 100 - 10 25 10 - 200 100
- - - - 45 -
100 10 15 10 - 200
- - - - 30 -
100 5 10 10 - 200
- - - - 25 -
70 5 10 10 - 200
- - - - 25 -
70 5 10 10 - 200
tCH tCHZ tCLH tCLR tCLS tCOH tCS tDH
20 - 20 20 50 0 70 20
- 100 - - - - - -
10 - 10 10 25 15 35 10
- 50 - - - - - -
10 - 10 10 15 15 25 5
- 50 - - - - - -
5 - 5 10 10 15 25 5
- 50 - - - - - -
5 - 5 10 10 15 20 5
- 30 - - - - - -
5 - 5 10 10 15 15 5
- 30 - - - - - -
ns ns ns ns ns ns ns ns 2
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Table 39: AC Characteristics: Asynchronous Command, Address, and Data (Continued)
Mode 0 Parameter Data setup time Output High-Z to RE# LOW RE# cycle time RE# access time RE# HIGH hold time RE# HIGH to output hold RE# HIGH to WE# LOW RE# HIGH to output High-Z RE# LOW to output hold RE# pulse width Ready to RE# LOW Device reset time (Read/Program/ Erase) WE# HIGH to R/B# LOW WE# cycle time WE# HIGH hold time WE# HIGH to RE# LOW WE# pulse width WP# transition to WE# LOW
tDS tIR tRC tREA tREH tRHOH tRHW tRHZ tRLOH tRP tRR tRST
Mode 1 20 0 50 - 15 15 100 - 0 25 20
-
Mode 2 15 0 35 - 15 15 100 - 0 17 20
-
Mode 3 10 0 30 - 10 15 100 - 0 15 20
-
Mode 4 10 0 25 - 10 15 100 - 5 12 20
-
Mode 5 7 0 20 - 7 15 100 - 5 10 20 - - - - 16 - - - 100 - - - 5/10/ 500 100 - - - - - ns ns ns ns ns ns ns ns ns ns ns s 4, 5 2, 3 3 3 3 3
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes 40 10 100 - 30 0 200 - 0 50 40
-
- - - 40 - - - 200 - - - 5/10/ 500 200 - - - - -
- - - 30 - - - 100 - - - 5/10/ 500 100 - - - - -
- - - 25 - - - 100 - - - 5/10/ 500 100 - - - - -
- - - 20 - - - 100 - - - 5/10/ 500 100 - - - - -
- - - 20 - - - 100 - - - 5/10/ 500 100 - - - - -
tWB tWC tWH tWHR tWP tWW
- 100 30 120 50 100
- 45 15 80 25 100
- 35 15 80 17 100
- 30 10 60 15 100
- 25 10 60 12 100
- 20 7 60 10 100
ns ns ns ns ns ns
6
Notes:
www..com
1. Timing for tADL begins in the address cycle, on the final rising edge of WE# and ends with the first rising edge of WE# for data input. 2. Data transition is measured 200mV from steady-steady voltage with load. This parameter is sampled and not 100 percent tested. 3. AC characteristics may need to be relaxed if output drive strength is not set to at least nominal. 4. If RESET (FFh) command is issued when the target is READY, the target goes busy for a maximum of 5s. 5. See Array Characteristics for details on the power-on reset time, tPOR. 6. Do not issue a new command during tWB, even if R/B# or RDY is ready.
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Electrical Specifications - AC Characteristics and Operating Conditions (Synchronous)
Table 40: AC Characteristics: Synchronous Command, Address, and Data
Mode 0 Parameter Clock period Frequency Access window of DQ[7:0] from CLK ALE to data loading time Command, address data delay ALE, CLE, W/R# hold ALE, CLE, W/R# setup DQ hold - command, address DQ setup - command, address Change column setup time to data in/out or next command CE# hold Average CLK cycle time
tAC
Mode 1 Max 30 33
Mode 2 Min Max 20 50
Mode 3 Min Max 15 67
Mode 4 Min Max 12 83
Mode 5 Min Max Unit 10 100 ns MHz ns 20 Notes
Symbol Min Max Min 50 20 10 20 10
20
10
20
10
20
10
20
10
tADL tCAD tCALH tCALS tCAH tCAS tCCS
100 25 10 10 10 10 200
- - - - - - -
100 25 5 5 5 5 200
- - - - - - -
70 25 4 4 4 4 200
- - - - - - -
70 25 3 3 3 3 200
- - - - - - -
70 25 2.5 2.5 2.5 2.5 200
- - - - - - -
70 25 2 2 2 2 200
- - - - - - -
ns ns ns ns ns ns ns 2 1
tCH tCK
10 50
- 100
5 30
- 50
tCK tCK
4 20
- 30
3 15
- 20
2.5 12
- 15
2 10
- 12
ns ns ns 3
(avg)
tCK (abs) Absolute CLK cycle time, from rising edge to rising edge
(abs) MIN = tCK (avg) + tJIT (per) MIN (abs) MAX = tCK (avg) + tJIT (per) MAX
CLK cycle HIGH CLK cycle LOW
tCKH
0.43 0.43
0.57 0.57
0.43 0.43
0.57 0.57
0.43 0.43
0.57 0.57
0.43 0.43
0.57 0.57
0.43 0.43
0.57 0.57
0.43 0.43
0.57 0.57
tCK tCK tCK
4 4
(abs)
tCKL
(abs)
tCKWR Data output end to W/R# www..com HIGH tCKWR(MIN)
= RoundUp[(tDQSCK(MAX) + tCK)/tCK]
CE# setup Data In hold
tCS tDH
35 5
- -
25 2.5
- -
15 1.7
- -
15 1.3
- -
15 1.1
- -
15 0.8
- -
ns ns
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Table 40: AC Characteristics: Synchronous Command, Address, and Data (Continued)
Mode 0 Parameter Access window of DQS from CLK DQS, DQ[7:0] Driven by NAND DQS, DQ[7:0] to tri-state DQS input high pulse width DQS input low pulse width DQS-DQ skew Data input Data In setup DQS falling edge from CLK rising - hold DQS falling to CLK rising - setup Data valid window Half clock period The deviation of a given tCK (abs) from a tCK (avg) DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data hold skew factor
tDQSCK
Mode 1 Max 20 -
Mode 2 Min - Max 20
Mode 3 Min - Max 20
Mode 4 Min - Max 20
Mode 5 Min Max Unit - 20 ns Notes
Symbol Min Max Min - 20
tDQSD tDQSHZ tDQSH tDQSL tDQSQ tDQSS tDS tDSH
- - 0.4 0.4 - 0.75 5 0.2
18 20 0.6 0.6 5 1.25 - -
- - 0.4 0.4 - 0.75 3 0.2
18 20 0.6 0.6 2.5 1.25 - -
- - 0.4 0.4 - 0.75 2 0.2
18 20 0.6 0.6 1.7 1.25 - -
- - 0.4 0.4 - 0.75 1.5 0.2
18 20 0.6 0.6 1.3 1.25 - -
- - 0.4 0.4 - 0.75 1.1 0.2
18 20 0.6 0.6 1.0 1.25 - -
- - 0.4 0.4 - 0.75 0.8 0.2
18 20 0.6 0.6 0.85 1.25 - -
ns ns
tCK tCK
5
ns
tCK
ns
tCK
tDSS
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
tCK
tDVW tHP tJIT
tDVW tHP
= tQH - tDQSQ
ns ns -0.6 0.6 -0.5 0.5 ns
= Min(tCKH, tCKL) 0.7 -0.6 0.6
(per) -0.7
0.7
-0.7
0.7
-0.7
tQH
tQH
= tHP - tQHS
ns
tQHS
- 100
6 -
- 100
3 -
- 100
2 -
- 100
1.5 -
- 100
1.2 -
- 100
1
ns ns
tRHW Data output to command, address, or data inwww..com put
Ready to data output
tRR
20
-
20
-
20
-
20
-
20
-
20
-
ns
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Table 40: AC Characteristics: Synchronous Command, Address, and Data (Continued)
Mode 0 Parameter Device reset time (Read/Program/Erase) CLK HIGH to R/ B# LOW Command cycle to data output DQS write preamble DQS write postamble W/R# LOW to data output cycle WP# transition to command cycle
tRST
Mode 1 Max 5/10/ 500 100 - - - - -
Mode 2 Min - Max 5/10/ 500 100 - - - -
Mode 3 Min - Max 5/10/ 500 100 - - - -
Mode 4 Min - Max 5/10/ 500 100 - - - -
Mode 5 Min Max Unit - 5/10/ 500 100 - - - - s Notes 6
Symbol Min Max Min - 5/10/ 500 100 - - - -
tWB tWHR tWPRE tWPST tWRCK
- 80 1.5 1.5 20
- 60 1.5 1.5 20
- 60 1.5 1.5 20
- 60 1.5 1.5 20
- 60 1.5 1.5 20
- 60 1.5 1.5 20
ns ns
tCK tCK
ns
tWW
100
-
100
-
100
-
100
-
100
-
100
-
ns
Notes:
1. Delay is from start of command to next command, address, or data cycle; start of address to next command, address, or data cycle; and end of data to start of next command, address, or data cycle. 2. This value is specified in the parameter page. 3. tCK(avg) is the average clock period over any consecutive 200-cycle window. 4. tCKH(abs) and tCKL(abs) include static offset and duty cycle jitter. 5. tDQSHZ begins when W/R# is latched HIGH by CLK. This parameter is not referenced to a specific voltage level; it specifies when the device outputs are no longer driving. 6. If RESET (FFh) is issued when the target is idle, the target goes busy for a maximum of 5s.
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Electrical Specifications - Array Characteristics
Table 41: Array Characteristics
Parameter Number of partial page programs ERASE BLOCK operation time Cache busy Dummy busy time Cache read busy time Busy time for SET FEATURES and GET FEATURES operations Busy time for interface change LAST PAGE PROGRAM operation time Busy time for OTP DATA PROGRAM operation if OTP is protected Power-on reset time PROGRAM PAGE operation time READ PAGE operation time Notes: Symbol NOP
tBERS tCBSY tDBSY tRCBSY tFEAT tITC tLPROG tOBSY tPOR tPROG tR
Typ - 0.7 3 0.5 3 - - - - - 230 -
Max 4 3.5 500 1 25 1 1 - 30 1 500 25
Unit Cycles ms s s s s s s s ms s s
Notes 1
2 3
1. The pages in the OTP Block have an NOP of 8. 2. tITC (MAX) is the busy time when the interface changes from asynchronous to synchronous using the SET FEATURES (EFh) command or synchronous to asynchronous using the RESET (FFh) command. During the tITC time, any command, including READ STATUS (70h) and READ STATUS ENHANCED (78h), is prohibited. 3. tLPROG = tPROG (last page) + tPROG (last page - 1) - command load time (last page) address load time (last page) - data load time (last page).
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Asynchronous Interface Timing Diagrams
Figure 73: RESET Operation
CLE
CE#
tWB
WE#
tRST
R/B#
DQ[7:0]
FFh RESET command
Figure 74: READ STATUS Cycle
tCLR CLE
tCLS
tCLH
CE#
tCS
tWP WE#
tCH
tCEA tWHR RE# tRHZ tDS tDH tIR tREA tRHOH tRP tCOH
tCHZ
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DQ[7:0] 70h
Status output
Don't Care
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Figure 75: READ STATUS ENHANCED Cycle
tCS
CE#
tCLS tCLH
CLE
tWC tWP tWP tWH tCH
WE#
tCEA tCHZ tCOH
tALH
tALS
tALH
tAR
ALE RE#
tRHZ tDS tDH tWHR tREA tRHOH
DQ[7:0]
78h
Row add 1
Row add 2
Row add 3
Status output
Don't Care
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Figure 76: READ PARAMETER PAGE
CLE WE# tWB ALE RE# tRR DQ[7:0] R/B# ECh 00h tR P00
tRP
tRC
P10
P2550
P01
Figure 77: READ PAGE
CLE CE#
tCLR
tWC
WE#
tWB
tAR
ALE
tR tRC tRHZ
RE#
tRR tRP
DOUT N DOUT N+1 DOUT M
DQx
00h
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
30h
Busy
RDY
Don't Care
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Figure 78: READ PAGE Operation with CE# "Don't Care"
CLE CE# RE#
ALE tR RDY
WE#
DQx
00h
Address (5 cycles)
30h
Data output
tCEA
CE#
tREA
RE#
tCHZ tCOH
Out
Don't Care
I/Ox
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams
Figure 79: CHANGE READ COLUMN
CLE
tCLR
CE# WE#
tRHW tCCS
ALE
tRC tREA
RE#
DQx
DOUT N-1
DOUT N
05h
Col add 1
Col add 2
E0h
DOUT M
DOUT M+1
Column address M
RDY
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Figure 80: READ PAGE CACHE SEQUENTIAL
CLE
tCLS tCS tCLH tCH tCLS tCS tCH tCLH
CE#
tWC
WE#
tCEA tRHW
ALE
tRC
RE#
tDH tDS tWB 00h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 30h tR 31h tRR tREA
DOUT 0 DOUT 1
tWB tDS
DOUT
tDH 31h
DQx
Column address 00h
Page address M
tRCBSY
Page address M
RDY
Column address 0
1
CLE
tCLS tCS tCH tCLH
CE#
WE#
tRHW tCEA tRHW
ALE
tRC tRC tWB tREA tDS
DOUT
RE#
tRR tDH 31h
tREA
DOUT 0 DOUT 1 DOUT
DQx
DOUT 0
DOUT 1
3Fh
DOUT 0
DOUT 1
DOUT
M www..com
Page address
tRCBSY
Page address M+1
tRCBSY
Page address M+2
RDY
Column address 0 Column address 0 Column address 0
1
Don't Care
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Figure 81: READ PAGE CACHE RANDOM
CLE
tCLS tCS tCLH tCH
CE#
tWC
WE#
ALE
RE#
tDH tDS
Col add 1 Col add 2 Row add 1 Row add 2 Row add 3
tWB 30h
tR 00h
Col add 1 Col add 2 Row add 1 Row add 2
DQx
00h
Column address 00h
Page address M
Column address 00h
Page address N
RDY
1
CLE
tCLS tCS
tCLH tCH
CE#
WE#
tCEA
tRHW
ALE
tWB tDS
Col add 1 Col add 2 Row add 1 Row add 2 Row add 3
tRC
RE#
tDH 31h
tRR
tREA
DOUT 0 DOUT 1 DOUT
3Fh
DQx
DOUT 0
DOUT 1
DOUT
Column address 00h
Page address N
tRCBSY
Page address M
tRCBSY
Page address N
www..com RDY
Column address 0
Column address 0
1
Don't Care
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams
Figure 82: READ ID Operation
CLE CE# WE#
tAR
ALE RE#
tWHR tREA
DQx
90h
00h or 20h Address, 1 cycle
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Figure 83: PROGRAM PAGE Operation
CLE CE#
tWC WE#
tADL
tWB ALE RE#
tPROG
tWHR
DQx
80h
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
DIN N
DIN M
10h
70h
Status
1 up to m byte serial Input RDY
Don't Care
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Figure 84: PROGRAM PAGE Operation with CE# "Don't Care"
CLE CE#
WE#
ALE DQx 80h Address (5 cycles) Data tCS
CE#
input tCH
Data
input
10h
tWP
WE#
Don't Care
Figure 85: PROGRAM PAGE Operation with CHANGE WRITE COLUMN
CLE CE# tWC WE# tWB ALE RE# tPROG tWHR tADL tCCS
DQx
80h
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
DIN M
DIN N
85h
Col add 1
Col add 2
DIN P
DIN Q Serial input
10h
70h
READ STATUS command
Status
Serial input
CHANGE WRITE Column address COLUMN command
RDY Don't Care
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams
Figure 86: PROGRAM PAGE CACHE
CLE CE#
tWC tADL
WE#
tWBtCBSY tWB tLPROG tWHR
ALE RE#
Row Row Row Col Col add 1 add 2 add 1 add 2 add 3 DIN DIN N M Serial input Col Col Row Row Row add 1 add 2 add 1 add 2 add 3 DIN N DIN M
DQx RDY
80h
15h
80h
10h
70h
Status
Last page - 1
Last page
Don't Care
Figure 87: PROGRAM PAGE CACHE Ending on 15h
CLE CE# tWC WE# tWHR ALE RE# DQx
Col Row Row Row Col add 1 add 2 add 1 add 2 add 3 DIN DIN M N Serial input Col Row Row Row Col add 1 add 2 add 1 add 2 add 3 DIN N DIN M
tADL
tADL
tWHR
80h
15h
70h
Status
80h
15h
70h
Status
70h
Status
Last page - 1
Last page
Poll status until: I/O6 = 1, Ready To verify successful completion of the last 2 pages: I/O5 = 1, Ready I/O0 = 0, Last page PROGRAM successful I/O1 = 0, Last page - 1 PROGRAM successful
Don't Care
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams
Figure 88: COPYBACK
CLE CE# tWC WE# tWB ALE RE# tR DQx RDY
00h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 35h (or 30h) 85h Col Row Row Row Col add 1 add 2 add 1 add 2 add 3 Data 1 Data N 10h 70h Status
tADL
tWB tPROG
tWHR
Busy
READ STATUS Busy command
Data Input Optional
Don't Care
Figure 89: ERASE BLOCK Operation
CLE CE#
tWC
WE#
tWB tWHR
ALE RE#
tBERS
DQ[7:0]
60h
Row add 1
Row add 2
Row add 3
D0h
70h READ STATUS command
Busy
Status
Row address
RDY
I/O0 = 0, Pass I/O0 = 1, Fail
Don't Care
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams
Synchronous Interface Timing Diagrams
Figure 90: SET FEATURES Operation
tCS CE#
CLE tCALS ALE tCAD CLK tDQSS W/R# tCAD tCAD tWB tFEAT tCALS
DQS
DQx
EFh
Feat Addr
P10
P11
P20
P21
P30
P31
P40
P41
R/B#
Don't Care
Notes:
1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the last data byte is input for the subsequent command or data input cycle(s). 2. tDSH (MIN) generally occurs during tDQSS (MIN). 3. tDSS (MIN) generally occurs during tDQSS (MAX). 4. The cycle that tCAD is measured from may be an idle cycle (as shown), another command cycle, an address cycle, or a data cycle. The idle cycle is shown in this diagram for simplicity.
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Figure 91: READ ID Operation
tCS CE# tCALS CLE
ALE tCAD CLK tCALS W/R# tDQSD DQS tDQSCK tCAD tWHR
tCALH
tCKWR tCALH
tRHW
tCALS
tDQSHZ
DQ[7:0]
90h
00h or 20h
Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4
Don't Care
Driven
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Figure 92: GET FEATURES Operation
tCS CE# tCALS CLE tCALS
ALE tCAD CLK tCALS W/R# tDQSD DQS tDQSCK tWRCK tCAD
tCALH
tCKWR tCALH tCALS
tRHW
tDQSHZ
DQ[7:0]
EEh
Feat Addr tWB tFEAT
P1
P2
P3
P4
RDY
Don't Care
Driven
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams
Figure 93: RESET (FCh) Operation
tCS tCH
CE#
tCALS tCALH
CLE
tCALS tCAD
tCALH
tCALH
ALE
CLK
W/R#
tWB
DQS
tCAS tCAH
DQ[7:0]
FCh SYNCHRONOUS RESET command
tRST
R/B#
Don't Care
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams
Figure 94: READ STATUS Cycle
CE#
CLE
ALE tWHR CLK tCAD W/R# tDQSD DQS tDQSHZ tCKWR tRHW
DQ[7:0]
70h READ STATUS command
Status
Status
RDY
Don't Care
Driven
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams
Figure 95: READ STATUS ENHANCED Operation
tCS CE#
CLE
ALE tCAD CLK tCAD W/R# tDQSD DQS tDQSHZ tCAD tCAD tCAD tWHR tCKWR tRHW
DQ[7:0]
78h
Row add 1
Row add 2
Row add 3
Status
Status
Don't Care
Driven
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Figure 96: READ PARAMETER PAGE Operation
tCS CE# tCALS CLE tCALS
ALE tCAD CLK tWRCK W/R# tDQSD DQS tDQSCK tCALS tDQSHZ tCKWR tCALH tRHW tCAD tCALH
DQ[7:0]
ECh
00h tWB tR
P0
P1
P2
Pn-3
Pn-2
Pn-1
Pn
RDY
Don't Care
Driven
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams
Figure 97: READ PAGE Operation
tCS
CE#
CLE ALE
tCAD tCAD tCAD tCAD tCAD tCAD tCAD
CLK
tCALS
W/R#
DQS Col add 1 Col add 2 Row add 1 Row add 2 Row add 3
DQx
00h
30h
tWB
tR
RDY
1
CE#
tCALS tCALS
CLE ALE
tCAD tCAD
tCALH
CLK
tCALS tWRCK tCKWR tCALH tRHW
W/R#
tDQSD tDQSCK tCALS tDQSHZ
DQS Row add 3
DQx
30h
tWB
Dout 0
Dout N-3
Dout N-2
Dout N-1
Dout N
tR
1 up to m Byte serial input
www..com RDY
1 Don't Care Driven
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Figure 98: CHANGE READ COLUMN
CE# tCALS CLE tCALS
ALE tRHW CLK tDQSD W/R# tDQSCK DQS tDQSHZ tCAD tCAD tCAD tCCS tRHW
DQx
05h
Col add 1
Col add 2
E0h
Dout C
Dout C+1
Dout D-2
Dout D-1
Dout D
RDY
Don't Care
Driven
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Figure 99: READ PAGE CACHE SEQUENTIAL (1 of 2)
CE#
CLE
ALE
tRHW
CLK
tDQSHZ
W/R#
tDQSD tDQSCK tDQSD
DQS Initial Read Data DQx 30h
tWB tR
31h
tWB
Data
tRCBSY
Output
31h
tWB
tRCBSY
RDY
Initial Read Access
Sequential Read Access A
Sequential Read Access B
1 Driven Don't Care
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Figure 100: READ PAGE CACHE SEQUENTIAL (2 of 2)
CE#
CLE
ALE
tRHW tRHW
CLK
tDQSHZ tDQSHZ
W/R#
tDQSD tDQSCK tDQSD tDQSCK
DQS Sequential Read Data A DQx
tRCBSY
Sequential Read Data B 3Fh
tRCBSY
Data
Output
Data
Output
tWB
RDY
1 Driven Don't Care
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Figure 101: READ PAGE CACHE RANDOM (1 of 2)
CE#
CLE ALE tRHW CLK tDQSHZ W/R# tDQSD DQS Initial Read Data DQx 30h tWB RDY tR 00h
5 Address Cycles
tCAD
tCAD x 4
tRHW
tCAD
tCAD x 4
tDQSCK
31h tWB tRCBSY
Data
Output
00h
5 Address Cycles
31h tRCBSY tWB
Initial Read Access
Random Read Access A
Random Read Access B
1 Don't Care Driven
Figure 102: READ PAGE CACHE RANDOM (2 of 2)
CE#
CLE ALE tCAD x 4 CLK tDQSHZ W/R# tDQSD DQS Random Read Data A DQx 31h tWB RDY tRCBSY
Data Output
tRHW
tRHW
tDQSHZ
tDQSCK
tDQSD
tDQSCK
Random Read Data B 3Fh tWB tRCBSY
Data Output
Read Access B www..com
Random
1 Don't Care Driven
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Figure 103: Multi-Plane Read Page (1 of 2)
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD x 5 tCAD tCAD x 5 tRHW tCAD tCAD x 5
CLK
tDQSHZ
W/R#
tDQSD tDQSCK
DQS If data from a plane other than A is desired, a 06h-E0h command sequence is required after tR and prior to taking W/R# LOW. 00h
Address B 5 Cycles
tWB
DQx
00h
Address A 5 Cycles
32h or 00h
30h
tWB tR
Data A Output
06h
Address B 5 Cycles
E0h
RDY Column and row addresses must be the same for all planes
tDBSY
1
Don't Care
Driven
2
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Figure 104: Multi-Plane Read Page (2 of 2)
CE#
CLE ALE
tRHW tCAD tCAD x 5
CLK
tDQSHZ
W/R#
tCCS tDQSD tDQSCK tDQSD tDQSCK
DQS
DQx
E0h
Data B Output
06h
Address A 5 Cycles
E0h
RDY
2
CE# CLE ALE
tRHW tCAD tCAD x 5 tRHW
3
CLK
tDQSHZ tDQSHZ
W/R#
tCCS tDQSCK tDQSD tDQSCK
DQS
Data A Output Address B 5 Cycles Data B Output
DQx www..com RDY
06h
E0h
3
Undefined (driven by NAND)
Don't Care
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Figure 105: PROGRAM PAGE Operation (1 of 2)
tCS CE#
CLE tCALS ALE tCAD CLK tCAD tCAD tCAD tCAD tCAD tADL tDQSS tCALS
W/R#
DQS Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 Din N Din N+1 Din M-2 Din M-1 Din M
DQx
80h
RDY
1
Don't Care
Driven
Figure 106: PROGRAM PAGE Operation (2 of 2)
CE#
CLE tCALS ALE tDQSS CLK tCAD W/R# tDQSD DQS Din N Din N+1 Din M-2 Din M-1 Din M tDQSHZ tCAD tWB tPROG tWHR tCKWR tRHW
DQx
10h
70h READ STATUS command
Status
Status
RDY
1
www..com
Don't Care
Driven
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Figure 107: CHANGE WRITE COLUMN
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD tCAD tCCS tDQSS
CLK
W/R#
DQS Din N+1 Din M-2 Din M-1 Din M Col add 1 Col add 2 Din C Din C+1
DQx
85h
RDY
1
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD tCAD tCCS tDQSS tCAD
CLK
W/R#
DQS Col add 1 Col add 2 Din C Din C+1 Din D-2 Din D-1 Din D
DQx
85h
www..com
RDY
1
Don't Care
Driven
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Figure 108: Multi-Plane Program Page
CE#
CLE
tCALS
tCALS
ALE
tCAD tCAD x 4 + tADL tDQSS tCAD tWB tDBSY tCAD
CLK W/R#
DQS Address A 5 Cycles Address B 5 Cycles
DQx RDY
80h
Data A
11h
80h
1
CE#
CLE ALE
tCAD tCAD x 4 + tADL tDQSS tCAD tWB tPROG tWHR tRHW
CLK
tCAD tDQSHZ
W/R#
tDQSD
DQS Address B 5 Cycles
DQx RDY
Data B
10h
70h
Status
Status
1
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Figure 109: ERASE BLOCK
tCS
CE# CLE
ALE
tCAD tCAD tCAD tCAD tCAD tWHR tRHW
CLK
tCAD
W/R#
tDQSD tDQSHZ
DQS
DQ[7:0]
60h
Row add 1
Row add 2
Row add 3
D0h
70h
Status Status
tWB
tBERS
READ STATUS command
RDY
Don't Care
Driven
Figure 110: COPYBACK (1 of 3)
CE#
CLE
ALE tCAD CLK tDQSHZ W/R# tDQSD DQS tDQSCK tCAD x 5 tRHW tCAD tCADx2
DQx
00h
5 Address Cycles
35h or 30h tWB tR
Data Output
05h
2 Address Cycles
E0h
RDY
www..com
Don't Care Driven 1
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Figure 111: COPYBACK (2 of 3)
CE#
CLE tCALS ALE tRHW CLK tDQSHZ W/R# tDQSD DQS tDQSCK tCAD tCAD x 5 tCAD tCAD + tADL tDQSS tCALS
DQx
h
Data Output
85h
5 Address Cycles
85h
2 Address Cycles
Data
RDY
1
Don't Care
Driven
2
Figure 112: COPYBACK (3 of 3)
CE#
CLE
ALE tCAD CLK tCAD W/R# tDQSD DQS tDQSHZ tWB tPROG tWHR tRHW
DQx
10h
70h
Status
Status
www..com
RDY
2
Don't Care
Driven
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Figure 113: READ OTP PAGE
tCS
CE#
tCALS
CLE
tCALS
ALE
tCALH tCAD tCAD tCAD tCAD tCAD tCAD tCAD
CLK
tCALS
W/R#
tWRCK
tCKWR tCALH
tRHW
tDQSD
DQS
tDQSCK
tCALS tDQSHZ
DQx
00h
Col add 1
Col add 2
OTP page1
00h
00h
30h
Dout 0
Dout N-3
Dout N-2
Dout N-1
Dout N
tWB tR
R/B#
Don't Care
Driven
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Figure 114: PROGRAM OTP PAGE (1 of 2)
tCS CE#
CLE tCALS ALE tCAD CLK tCAD tCAD tCAD tCAD tCAD tADL tDQSS tCALS
W/R#
DQS
DQx
80h
Col add 1
Col add 2
OTP page1
00h
00h
Din N
Din N+1
Din M-2
Din M-1
Din M
RDY
Don't Care
Driven
1
Figure 115: PROGRAM OTP PAGE (2 of 2)
CE#
CLE tCALS ALE tCAD CLK tCAD W/R# tDQSD DQS tDQSHZ tWB tPROG tWHR tCKWR tRHW
DQx
Din M-2
Din M-1
Din M
10h
70h READ STATUS command
Status
Status
www..com
RDY
OTP data written (following "pass" status confirmation)
1
Don't Care
Driven
Transitioning
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Figure 116: PROTECT OTP AREA
CE# CLE
tCALS
ALE
tCAD tCAD tCAD tCAD tCAD tCAD tADL tDQSS
CLK
W/R# DQS
DQ[7:0]
80h
Col 00h
Col 00h
01h
00h
00h
00h
RDY
1
CE# CLE ALE
tCALS
tCAD
tWB
tPROG
tWHR
tRHW
CLK
tCAD tDQSHZ
W/R#
tDQSD
DQS DQ[7:0] 10h 70h READ STATUS command
Status Status
www..com
RDY
1
Don't Care
Driven
Transitioning
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16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Revision History
Revision History
Rev. E, Production - 3/10
* Corrected typo in "Error Management Details" and "Valid Blocks per LUN" tables for number of valid blocks (NVB) from 3996 to 4016.
Rev. D, Production - 1/10
* Removed OCPL "WC" TSOP package option * Changed tBERS MAX from 3ms to 3.5ms * Updated values of "Parameter Page Data Structure" for changes to tBERS
Rev. C - 9/09
* * * * * * * * * * * Updated ONFI compliance from 2.0 to 2.1 standard Added "H2" BGA package option Added 128Gb BGA package option and references to this configuration Added 64Gb BGA/LGA four CE# package option and references to this configuration Removed 32Gb LGA package option and references to this configuration Updated values of "Parameter Page Data Structure" Updated definition of tFALL and tRISE Defined values for ICC4, ICC5, ICC6, and ISBQ Updated package capacitance values for BGA, LGA, and TSOP packages Updated "Test Conditions" table Changed tPROG TYP from 200s to 230s
Rev. B - 2/09
* Removed text `SET FEATURES selects asynchronous/synchronous mode for data input/output' from "Features" * Changed `PA7' to `BA7' in "Array Addressing for 16Gb Logical Unit (LUN)" table; under table, changed note 4 to reference `BA[7]' instead of `BA[8]' * Added column `I/O[7:0] DQ[7:0]' and changed the heading `WP' to `WP#' in "Asynchronous Interface Mode Selection" table * Changed Y-axis units for "IOL vs. Rp (VccQ = 3.3V)" figure * Changed Y-axis units for "TC vs. Rp" figure * Changed `1ms' to `tPOR' in step 6 under "Vcc Power Cycling" * Added optional 11h command and note 8 to CHANGE ROW ADDRESS in "Command Set" table * Added `1' to column `# Valid Address Cycles' for READ UNIQUE ID command in "Command Set" table * Added text to second paragraph of "SYNCHRONOUS RESET (FCh)" on to more closely line up with "RESET (FFh)" * Updated `Edh' to `EDh' in "READ UNIQUE ID (EDh) Operation" figure * Corrected SELECT LUN WITH STATUS (70h) to (78h) for RDY in "Status Register Definition" table * Removed text describing data output/input from "CHANGE WRITE COLUMN (85h)" and added that text to "CHANGE ROW ADDRESS (85h)" 157
Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2009 Micron Technology, Inc. All rights reserved.
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PDF: 09005aef838cada2 Rev. E 3/10 EN
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Revision History
* Removed first two bullets of text under "CHANGE WRITE COLUMN (85h)" and "CHANGE ROW ADDRESS (85h)" * Changed `CHANGE WRITE COLUMN' to `CHANGE ROW ADDRESS' under "READ Operations" * Added text describing not to use a READ PAGE CACHE SEQUENTIAL (31h) command to cross LUN boundaries to "READ PAGE CACHE SEQUENTIAL (31h)" * Updated the following under "Multi-Plane Addressing" on page 93: Changed second bullet from referencing `BA[8]' to `BA[7]'; Changed third bullet from referencing `PA[7:0]' to `PA[6:0]' * Broke out load test conditions for different values of VccQ in "Test Conditions" table * Changed references to tWC to tCK in "Synchronous Device DC and Operating Characteristics" table * Updated description of tCCS parameter in "AC Characteristic: Synchronous Command, Address, and Data" table and "AC Characteristics: Asynchronous Command, Address, and Data" table
Rev. A - 1/09
* Initial release
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PDF: 09005aef838cada2 Rev. E 3/10 EN
158
Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2009 Micron Technology, Inc. All rights reserved.

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